Abstract: A thermal simulation device is applied to a transaction-level designed chip which includes a plurality of intellectual properties. The thermal simulation device includes a plurality of thermal-aware transaction-level power model circuits, a simulator, a translator and a thermal emulator. The thermal-aware transaction-level power model circuits corresponds to the respective intellectual properties, and are configured to a corresponding power information for each of the intellectual properties, and dynamically adjusts the power information according to temperature information. The simulator is configured to generate the corresponding temperature information of the intellectual properties according to compatible information. The translator is configured to generate the compatible information which is compatible with the simulator. The thermal emulator is configured to trigger the simulator and transmit the temperature information to the intellectual properties.

Abstract: A method for system simulation includes the steps of: simulating the operation of a first circuit during N clock periods based on a first model and a simulation granularity, and adjusting the simulation granularity based on the input signal or the output signal corresponding to the first model. A non-transitory computer-readable recording medium corresponding to the method is also provided.

Abstract: A thermal simulation device is applied to a transaction-level designed chip which includes a plurality of intellectual properties. The thermal simulation device includes a plurality of thermal-aware transaction-level power model circuits, a simulator, a translator and a thermal emulator. The thermal-aware transaction-level power model circuits corresponds to the respective intellectual properties, and are configured to a corresponding power information for each of the intellectual properties, and dynamically adjusts the power information according to temperature information. The simulator is configured to generate the corresponding temperature information of the intellectual properties according to compatible information. The translator is configured to generate the compatible information which is compatible with the simulator. The thermal emulator is configured to trigger the simulator and transmit the temperature information to the intellectual properties.

Abstract: An analyzing method and an analyzing system for graphics process are provided. The analyzing method includes the following steps. A graphics application program is provided and a plurality of graphics parameters of the graphics application program are obtained. The graphics application program is classified to be at least one of a plurality of groups according to the graphics parameters. A plurality weighting coefficients are obtained. A total loading of a graphics processing unit for performing the graphics application program is calculated according to the weighting coefficients and the graphics parameters.

Abstract: A scheduling method is provided. The method includes: recording a next instruction and a ready state of each thread group in a scoreboard; determining whether there is any ready thread group whose ready state is affirmative; determining whether a load/store unit is available, wherein the load/store unit is configured to access a data memory unit; when the load/store unit is available, determining whether the ready thread groups include a data access thread group, wherein the next instruction of the data access thread group is related to accessing the data memory unit; selecting a target thread group from the data access thread groups; and dispatching the target thread group to the load/store unit for execution.

Abstract: A data-processing apparatus and an operation method thereof are provided. The data-processing apparatus includes a tiling circuit and a post-stage processing circuit. The tiling circuit is configured to receive input data. The tiling circuit divides a current frame of the input data into at least one tile and checks a motion state of the current tile in the at least one tile. The post-stage processing circuit is coupled to the tiling circuit to receive the current tile. The post-stage processing circuit performs post processing on the current tile to generate a processed current tile of the current frame or to obtain a processed corresponding tile of a previous frame and serves it as the processed current tile of the current frame, according to the motion state of the current tile.

Abstract: A NoC timing power estimating method includes: estimating a plurality of transmission timing of a plurality of transmission units of at least a packet, the transmission timing indicating respective time points at which the transmission units enter/leave a plurality of passing elements of the NoC; based on the transmission timing of the transmission units, estimating respective circuit states and respective power states of the passing elements of the NoC, the circuit state indicating an operation state of the passing element and the power state being related to the circuit state; and based on the power states of the passing elements of the NoC, estimating power consumption of the NoC.

Abstract: A data-processing apparatus and an operation method thereof are provided. The data-processing apparatus includes a tiling circuit and a post-stage processing circuit. The tiling circuit is configured to receive input data. The tiling circuit divides a current frame of the input data into at least one tile and checks a motion state of the current tile in the at least one tile. The post-stage processing circuit is coupled to the tiling circuit to receive the current tile. The post-stage processing circuit performs post processing on the current tile to generate a processed current tile of the current frame or to obtain a processed corresponding tile of a previous frame and serves it as the processed current tile of the current frame, according to the motion state of the current tile.

Abstract: A memory controlling device and method are disclosed for controlling a memory having a partial array self refresh (PASR) function and a plurality of memory segments. The memory controlling device comprises an address mapper, an address decoder, an address selector, and a PASR configuration register storing a PASR configuration. The address mapper converts an input address set into a mapped address set according to an address offset. The mapped address set comprises a plurality of consecutive mapped addresses or at least one mapped address within a limited range. The address decoder updates the PASR configuration during writing. The address selector generates an updated address set, which is used for setting at least one mode register of the memory, according to the PASR configuration register under a sleep-or-standby mode in order that the memory can self refresh at least one of the memory segments correspondingly.