Abstract: A semiconductor structure is provided in which a phase change memory (PCM) device region including a PCM is located in a back side of a wafer. A PCM device back side source/drain contact structure connects the PCM to a first source/drain structure of a first field effect transistor (FET) that is present in a front side of the wafer, the second source/drain structure of the first FET is connected to a front side BEOL structure by a front side source/drain contact structure. A logic device region and/or an analog device region can be located laterally adjacent to the PCM device region. A back side power distribution network can be present in the logic device region and/or an analog device region.

Abstract: Backside and frontside contact structures wrapping around source/drain regions provide increased contact areas for electrical connections and allow increased silicide areas. Sidewall metallization of epitaxially grown source/drain regions provides source/drain sidewall contacts that enable wrap-around contact formation on both the front side and the back side of a semiconductor device layer. Front side and back side contact metallization over the source/drain sidewall contacts allows wrap-around contact structures on both sides of the device layer.

Abstract: A semiconductor structure is presented including a first dielectric isolation pillar disposed between a pair of p-type field effect transistors (pFETs), a second dielectric isolation pillar disposed between a pair of n-type FETs (nFETs), a first source/drain (S/D) epi region having a first contact electrically connected to a backside power delivery network (BSPDN), the first contact being disposed on one side of the first dielectric isolation pillar, and a second S/D epi region having a second contact electrically connected to back-end-of-line (BEOL) components, the second contact being disposed on the other side of the first dielectric isolation pillar.

Abstract: Backside self-aligned contact designs using a replacement contact process with unique placeholder profile are provided. In one aspect, a semiconductor device includes: a field-effect transistor(s) on a frontside of the device; backside power rails on a backside of the device; a backside source/drain region contact connecting a given one of the backside power rails to a source/drain region of the field-effect transistor(s), and a dielectric placeholder(s) between the given backside power rail and another source/drain region of the field-effect transistor(s), where a first end of the dielectric placeholder(s) having a width W1 directly contacts the given backside power rail, a second end of the dielectric placeholder(s) having a width W2 directly contacts the other source/drain region, where W1>W2. The field-effect transistor(s) can include a stack of active layers with bottom dielectric isolation, and a gate-all-around configuration.

Abstract: A semiconductor structure is provided that includes a first pair of stacked devices located in a first active device region and a second pair of stacked devices located in a second active device region. Each stacked device of the pair of stacked devices includes a second field effect transistor (FET) stacked over a first FET, and within each active device region the pair of stacked devices is separated by an inter-device dielectric pillar. A local interconnect structure is located in a non-active device region that is positioned between the first and second active device regions. The local interconnect structure can be connected to a back side power rail and a source/drain region of one of the second FETs, or connected to a front side signal line and a source/drain region of one of the first FETs.

Abstract: A semiconductor structure is presented including a first source/drain (S/D) epi region having a first contact completely wrapping around the first S/D epi region, the first contact electrically connected to a backside power delivery network (BSPDN) and a second S/D epi region having a second contact directly contacting a first sidewall, a second sidewall, and a top surface of the second S/D epi region, the second contact electrically connected to back-end-of-line (BEOL) components.

Abstract: Techniques for co-integrating gate-all-around nanosheet devices having bottom dielectric isolation with an ideal vertical P-N-P diode on a common substrate are provided. In one aspect, a semiconductor structure includes: a diode in a first region of a bulk substrate, where the diode includes P-N-P vertical implanted layers present in the bulk substrate, and a single source/drain region epitaxial material disposed on the P-N-P vertical implanted layers; and a nanosheet device with a bottom dielectric isolation layer in a second region of the bulk substrate. The nanosheet device can include nanosheet channels and gates that surround a portion of each of the nanosheet channels in a gate-all-around configuration. A method of fabricating the present semiconductor structures is also provided.

Abstract: A complementary field effect transistor (CFET) structure including a first transistor disposed above a second transistor, a first source/drain region of the first transistor disposed above a second source/drain region of the second transistor, wherein the first source/drain region comprises a smaller cross-section than the second source/drain region, a first dielectric material disposed in contact with a bottom surface and vertical surfaces of the first source/drain region and further in contact with a vertical surface and top surface of the second source/drain region, and a second dielectric material disposed as an interlayer dielectric material encapsulating the first and second transistors.

Abstract: A long channel transistor structure including a first transistor array adjacent to a second transistor array, a third transistor array adjacent to a fourth transistor array, where the third transistor array and the fourth transistor array are arranged above the first transistor array and the second transistor array, and a continuous channel path through channels of the first transistor array, the second transistor array, the third transistor array, and the fourth transistor array.

Abstract: Embodiments of present invention provide a ferroelectric random-access memory (FeRAM) cell. The FeRAM cell includes a vertical channel between a bottom source/drain region and a top source/drain region; a gate oxide surrounding the vertical channel; and a ferroelectric layer surrounding the gate oxide, wherein the ferroelectric layer has two or more sections of different horizontal thicknesses between the bottom source/drain region and the top source/drain region. A method of manufacturing the FeRAM cell is also provided.

Abstract: A semiconductor structure comprises one or more transistor devices on a first side of the semiconductor structure, one or more transistor devices on a second side of the semiconductor structure, the second side being opposite the first side, and a dielectric isolation layer separating the one or more transistor devices on the first side of the semiconductor structure from the one or more transistor devices on the second side of the semiconductor structure. The one or more transistor devices on the second side of the semiconductor structure comprise channel layers on one side of the dielectric isolation layer and source/drain regions that are independent of source/drain regions of the one or more transistor devices on the first side of the semiconductor structure.

Abstract: Semiconductor devices, integrated chips, and methods of forming the same include forming a fill over a stack of semiconductor layers. The stack of semiconductor layers includes a first sacrificial layer and a set of alternating second sacrificial layers and channel layers. A dielectric fin is formed over the stack of semiconductor layers. The first sacrificial layer and the second sacrificial layers are etched away, leaving the channel layers supported by the dielectric fin over an exposed substrate surface. A dielectric layer is conformally deposited on the exposed substrate surface, the dielectric layer having a consistent thickness across the top surface. A conductive material is deposited over the dielectric layer.

Abstract: Disclosed is a structure for implementing a Physically Unclonable Function (PUF)-based random number generator and a method for forming the structure. The structure includes same-type, same-design devices in a semiconductor layer. While values of a performance parameter exhibited by some devices (i.e., first devices) are within a range established based on the design, values of the same performance parameter exhibited by other devices (i.e., second devices) is outside that range. A random distribution of the first and second devices is achieved by including randomly patterned dopant implant regions in the semiconductor layer. Each first device is separated from the dopant implant regions such that its performance parameter value is within the range and each second device has a junction with dopant implant region(s) such that its performance parameter value is outside the range or vice versa. A random number generator can be operably connected to the devices to generate a PUF-based random number.

Abstract: A non-volatile memory having a 3D cross-point architecture and twice the cell density is provided in which vertically stacked word lines run in plane (i.e., parallel) to the substrate and bit lines runs perpendicular to the vertically stacked word lines. The vertically stacked word lines are located in a patterned dielectric material stack that includes alternating first dielectric material layers and recessed second dielectric material layers. The first dielectric material layers vertically separate each word line within each vertical stack of word lines and the recessed second dielectric material layers are located laterally adjacent to the word lines. A dielectric switching material layer is located between each word line-bit line combination. Some of the bit lines are located in the dielectric material stack and some of the bit lines are located in an interlayer dielectric material layer.

Abstract: A CFET (complementary field effect transistor) structure including a substrate, a first CFET formed above the substrate, and a second CFET formed above the substrate. The first CFET includes a top FET and a bottom FET. The top FET and bottom FET of the first CFET include at least one nanosheet channel. A gate affiliated with the first CFET and the second CFET devices includes a continuous horizontal dielectric over the entire length of the gate. The top FET of each CFET has a first polarity. The bottom FET of each a CFET comprises a second polarity. The top FET of the first CFET includes a first work function metal, and the top FET of the second CFET includes a second work function metal.

Abstract: A phase change memory (PCM) structure including a bottom electrode, a first dielectric spacer disposed above and in contact with the bottom electrode, the first dielectric spacer comprising a vertical seam, a PCM layer disposed above the first dielectric spacer, and a heater element disposed in the seam and in contact with the bottom electrode.

Abstract: Embodiments of present invention provide a SRAM device. The SRAM device includes a first, a second, and a third SRAM cell each having a first and a second pass-gate (PG) transistor, wherein the second PG transistor of the second SRAM cell and the first PG transistor of the first SRAM cell are stacked in a first PG transistor cell, and the first PG transistor of the third SRAM cell and the second PG transistor of the first SRAM cell are stacked in a second PG transistor cell. The first and second PG transistors of the first SRAM cell may be stacked on top of, or underneath, the second PG transistor of the second SRAM cell and/or the first PG transistor of the third SRAM cell.

Abstract: A semiconductor device is provided. The semiconductor device includes a first field effect device on a first region of a substrate, wherein a first gate structure and an electrostatic discharge device on a second region of the substrate, wherein a second gate structure for the electrostatic discharge device is separated from the substrate by the bottom dielectric layer, and a second source/drain for the electrostatic discharge device is in electrical contact with the substrate, wherein the second source/drain is doped with a second dopant type.

Abstract: A microelectronic structure comprises a first stacked device structure comprising a first upper device and a first lower device, a second stacked device structure comprising a second upper device and a second lower device, and an isolation pillar structure located between the first and second stacked device structures. The isolation pillar structure has an upper section contacting the first and second upper devices and a lower section contacting the first and second lower devices. The upper section of the isolation pillar structure has a first width and the lower section of the isolation pillar structure has a second width different than the first width.

Abstract: A magnetic shielding structure for protecting an MRAM array from adverse switching effects due to external magnetic fields of neighboring devices is provided. The magnetic shielding structure includes a bottom magnetic shield material-containing layer and a top magnetic shield material-containing layer within the MRAM array. The bottom and top magnetic shield material-containing layers can be connected by a vertical magnetic shield containing-material layer that is located near each end of the bottom and top magnetic shield material-containing layers. The bottom magnetic shield material-containing layer is located beneath a MTJ pillar of each MRAM device, but above, bottom electrically conductive structures that are in electrical contact with the MRAM devices. The top magnetic shield material-containing layer is located above the MRAM devices, and is located laterally adjacent to, but not above or below, top electrically conductive structures that are also in electrical contact with the MRAM devices.