Patents by Inventor Jumpei Sato

Jumpei Sato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10854244
    Abstract: A semiconductor memory device includes n interconnect layers above a substrate; and a first interconnect region between an end of a control circuit and an end of the substrate in a direction of a first axis beside a first pad region in a direction of a second axis. The n interconnect layers are located at different levels from the substrate. Each of the n interconnect layers includes an interconnect. The first interconnect region includes no transistor, and no contact coupled to the substrate. The first interconnect region includes an interconnect extending along the second axis in m (m is a natural number equal to or larger than 3, larger than n/2, and equal to or smaller than n) interconnect layers of the n interconnect layers.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: December 1, 2020
    Assignee: Toshiba Memory Corporation
    Inventor: Jumpei Sato
  • Patent number: 10699814
    Abstract: The task is to provide a system which supports smooth patient referral from a referral source medical institution to a referral destination medical institution and which particularly prevents readmission due to cases that are difficult to determine simply based on patient attributes or due to the quality of medical services. To achieve this task, a referral difficult degree calculation unit calculates a referral difficulty degree which quantifies the risk that a patient cannot be discharged because a referral destination cannot be found, in consideration of a readmission risk calculated by a readmission risk calculation unit, the geographical distance between the patient and the referral destination medical institution, the total number of patients accepted, and the number of beds available. This referral difficulty degree is outputted to an output unit of the referral source medical institution or the referral destination medical institution.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: June 30, 2020
    Assignee: Hitachi, Ltd.
    Inventors: Shuntaro Yui, Jumpei Sato, Kunihiko Kido, Takuya Kamiyama
  • Patent number: 10645266
    Abstract: A stereo image pickup unit includes: first and second image pickup apparatuses including first and second image pickup devices and first and second mount boards, the image pickup apparatuses being formed in a same shape each other; and a holding frame for holding the first and second image pickup devices, the first and second mount boards including non-mounting surfaces perpendicular to rear surfaces of the first and second image pickup devices and projecting toward an outer side of projection surfaces of the first and second image pickup devices, the holding frame holding the first and second image pickup apparatuses such that the non-mounting surfaces are opposed to each other on a parallax direction inner side.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: May 5, 2020
    Assignee: OLYMPUS CORPORATION
    Inventors: Hirokazu Ichihara, Hiroshi Unsai, Toshiyuki Fujii, Mayumi Imai, Teruyuki Nishihara, Jumpei Arai, Masahiro Sato
  • Patent number: 10622033
    Abstract: According to one embodiment, a semiconductor storage device includes: a memory cell array including a plurality of bit lines; a sense amplifier; a first circuit including a plurality of transistors respectively connected to the plurality of bit lines and the sense amplifier; and a plurality of interconnects which are provided at a position higher than the bit lines in the first circuit and are not directly connected to the first circuit. The semiconductor storage device does not include, at a position higher than the plurality of interconnects, an interconnect which electrically connects two positions in the semiconductor storage device.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: April 14, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Jumpei Sato
  • Publication number: 20200013435
    Abstract: A semiconductor memory device includes n interconnect layers above a substrate; and a first interconnect region between an end of a control circuit and an end of the substrate in a direction of a first axis beside a first pad region in a direction of a second axis. The n interconnect layers are located at different levels from the substrate. Each of the n interconnect layers includes an interconnect. The first interconnect region includes no transistor, and no contact coupled to the substrate. The first interconnect region includes an interconnect extending along the second axis in m (m is a natural number equal to or larger than 3, larger than n/2, and equal to or smaller than n) interconnect layers of the n interconnect layers.
    Type: Application
    Filed: September 17, 2019
    Publication date: January 9, 2020
    Applicant: Toshiba Memory Corporation
    Inventor: Jumpei SATO
  • Patent number: 10460770
    Abstract: A semiconductor memory device includes n interconnect layers above a substrate; and a first interconnect region between an end of a control circuit and an end of the substrate in a direction of a first axis beside a first pad region in a direction of a second axis. The n interconnect layers are located at different levels from the substrate. Each of the n interconnect layers includes an interconnect. The first interconnect region includes no transistor, and no contact coupled to the substrate. The first interconnect region includes an interconnect extending along the second axis in m (m is a natural number equal to or larger than 3, larger than n/2, and equal to or smaller than n) interconnect layers of the n interconnect layers.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: October 29, 2019
    Assignee: Toshiba Memory Corporation
    Inventor: Jumpei Sato
  • Publication number: 20190295603
    Abstract: A semiconductor memory device includes n interconnect layers above a substrate; and a first interconnect region between an end of a control circuit and an end of the substrate in a direction of a first axis beside a first pad region in a direction of a second axis. The n interconnect layers are located at different levels from the substrate. Each of the n interconnect layers includes an interconnect. The first interconnect region includes no transistor, and no contact coupled to the substrate. The first interconnect region includes an interconnect extending along the second axis in m (m is a natural number equal to or larger than 3, larger than n/2, and equal to or smaller than n) interconnect layers of the n interconnect layers.
    Type: Application
    Filed: August 13, 2018
    Publication date: September 26, 2019
    Applicant: Toshiba Memory Corporation
    Inventor: Jumpei SATO
  • Patent number: 10395766
    Abstract: Upon evaluation of a value of a diagnostic process, the value of a diagnostic process is evaluated not based on a simple cost but on a cost required for all processes of a patient who was in the diagnostic process through a follow-up survey. Diagnostic processes that are not relevant to a target diagnostic process are eliminated, clustering is performed on patients to divide the patients into clinically meaningful homogeneous groups, and the target diagnostic process is evaluated for each of the homogeneous groups. For the purpose, importance scores of data pieces of the clinical data are calculated and the relevant data is output using the output result of the medical knowledge extraction unit, clustering is performed on patients in the clinical data, and a clinical index and a cost are output for each of the clusters.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: August 27, 2019
    Assignee: Hitachi, Ltd.
    Inventors: Syuntaro Yui, Kunihiko Kido, Kazuyuki Shimada, Masayuki Ohta, Jumpei Sato, Toru Hisamitsu
  • Publication number: 20190199895
    Abstract: A stereo image pickup unit includes: first and second image pickup apparatuses including first and second image pickup devices and first and second mount boards, the image pickup apparatuses being formed in a same shape each other; and a holding frame for holding the first and second image pickup devices, the first and second mount boards including non-mounting surfaces perpendicular to rear surfaces of the first and second image pickup devices and projecting toward an outer side of projection surfaces of the first and second image pickup devices, the holding frame holding the first and second image pickup apparatuses such that the non-mounting surfaces are opposed to each other on a parallax direction inner side.
    Type: Application
    Filed: March 1, 2019
    Publication date: June 27, 2019
    Applicant: OLYMPUS CORPORATION
    Inventors: Hirokazu ICHIHARA, Hiroshi UNSAI, Toshiyuki FUJII, Mayumi IMAI, Teruyuki NISHIHARA, Jumpei ARAI, Masahiro SATO
  • Patent number: 10303085
    Abstract: Provided is an electrophotographic photosensitive member capable of achieving both high leak resistance and reduction in variations in dark part potential and bright part potential due to repeated use even when CB is used for an electrically conductive layer. An electrophotographic photosensitive member including: a support, an electrically conductive layer, and a photosensitive layer, sequentially, wherein the electrically conductive layer contains a binder resin and carbon black, a number average primary particle diameter of the carbon black is 200 nm or more and 500 nm or less, an average inter-particle distance of the carbon black is 200 nm or more and 600 nm or less, a coefficient of variation of an inter-particle distance is 1.2 or less, and SF-1 of the carbon black is 150 or less.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: May 28, 2019
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Taichi Sato, Jumpei Kuno, Kenichi Kaku, Takashi Anezaki, Atsushi Fujii
  • Publication number: 20190157475
    Abstract: A solar cell element is provided with a semiconductor substrate, a passivation layer, and an electrode. The semiconductor substrate has a first surface and a second surface that is positioned on a back side of the first surface. The passivation layer is positioned on the second surface of the semiconductor substrate. The electrode is positioned on the passivation layer and positioned in the state of being electrically connected to the semiconductor substrate. The electrode includes a linear electrode part that is positioned along a peripheral edge of the semiconductor substrate when the semiconductor substrate is seen from the second surface side in plane perspective view, and is positioned in the state of penetrating the passivation layer in a thickness direction.
    Type: Application
    Filed: January 23, 2019
    Publication date: May 23, 2019
    Inventors: Jumpei SATO, Akira MURAO, Norihiko MATSUSHIMA
  • Publication number: 20180268877
    Abstract: According to one embodiment, a semiconductor storage device includes: a memory cell array including a plurality of bit lines; a sense amplifier; a first circuit including a plurality of transistors respectively connected to the plurality of bit lines and the sense amplifier; and a plurality of interconnects which are provided at a position higher than the bit lines in the first circuit and are not directly connected to the first circuit. The semiconductor storage device does not include, at a position higher than the plurality of interconnects, an interconnect which electrically connects two positions in the semiconductor storage device.
    Type: Application
    Filed: February 13, 2018
    Publication date: September 20, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventor: Jumpei SATO
  • Publication number: 20170294548
    Abstract: An insulating paste includes a siloxane resin and an organic solvent. The siloxane resin includes a phenyl group and an alkyl group expressed by a general formula CnH2n+1, in which n is a natural number. The number of alkyl groups is greater than the number of phenyl groups in the siloxane resin.
    Type: Application
    Filed: April 11, 2017
    Publication date: October 12, 2017
    Inventors: Jumpei SATO, Ryo MATSUOKA, Shinya ISHIKAWA
  • Patent number: 9639649
    Abstract: According to one embodiment, a semiconductor memory device includes a core section, a corner area adjacent section, a first circuit block and a second circuit block, and multiple wiring layers. The corner area adjacent section is arranged adjacently to a corner area positioned in a corner of the core section adjacently to the sense amplifier and the row decoder. The multiple wiring layers are provided in each of the first circuit block and the second circuit block, wherein a first wire in one of the multiple wiring layers in the first circuit block is arranged parallel to a second wire included in a wiring layer in the second circuit block which is the same as the wiring layer of the first wire.
    Type: Grant
    Filed: November 11, 2015
    Date of Patent: May 2, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tsuyoshi Etou, Jumpei Sato, Satoshi Yamano, Osamu Ooto, Souichi Minemura
  • Publication number: 20170053053
    Abstract: According to one embodiment, a semiconductor memory device includes a core section, a corner area adjacent section, a first circuit block and a second circuit block, and multiple wiring layers. The corner area adjacent section is arranged adjacently to a corner area positioned in a corner of the core section adjacently to the sense amplifier and the row decoder. The multiple wiring layers are provided in each of the first circuit block and the second circuit block, wherein a first wire in one of the multiple wiring layers in the first circuit block is arranged parallel to a second wire included in a wiring layer in the second circuit block which is the same as the wiring layer of the first wire.
    Type: Application
    Filed: November 11, 2015
    Publication date: February 23, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tsuyoshi ETOU, Jumpei SATO, Satoshi YAMANO, Osamu OOTO, Souichi MINEMURA
  • Publication number: 20150310184
    Abstract: The task is to provide a system which supports smooth patient referral from a referral source medical institution to a referral destination medical institution and which particularly prevents readmission due to cases that are difficult to determine simply based on patient attributes or due to the quality of medical services. To achieve this task, a referral difficult degree calculation unit calculates a referral difficulty degree which quantifies the risk that a patient cannot be discharged because a referral destination cannot be found, in consideration of a readmission risk calculated by a readmission risk calculation unit, the geographical distance between the patient and the referral destination medical institution, the total number of patients accepted, and the number of beds available. This referral difficulty degree is outputted to an output unit of the referral source medical institution or the referral destination medical institution.
    Type: Application
    Filed: December 21, 2012
    Publication date: October 29, 2015
    Inventors: Shuntaro YUI, Jumpei SATO, Kunihiko KIDO, Takuya KAMIYAMA
  • Publication number: 20150278459
    Abstract: Upon evaluation of a value of a diagnostic process, the value of a diagnostic process is evaluated not based on a simple cost but on a cost required for all processes of a patient who was in the diagnostic process through a follow-up survey. Diagnostic processes that are not relevant to a target diagnostic process are eliminated, clustering is performed on patients to divide the patients into clinically meaningful homogeneous groups, and the target diagnostic process is evaluated for each of the homogeneous groups. For the purpose, importance scores of data pieces of the clinical data are calculated and the relevant data is output using the output result of the medical knowledge extraction unit, clustering is performed on patients in the clinical data, and a clinical index and a cost are output for each of the clusters.
    Type: Application
    Filed: June 28, 2013
    Publication date: October 1, 2015
    Inventors: Syuntaro Yui, Kunihiko Kido, Kazuyuki Shimada, Masayuki Ohta, Jumpei Sato, Toru Hisamitsu
  • Patent number: 9024444
    Abstract: In a semiconductor device, a first contact-diffusion-layer is in a first well to be connected to the first well and extends in a channel width direction of a first transistor in a first well. A second contact-diffusion-layer is in the first well so as to be electrically connected to the first well and extends in a channel-length direction of the first transistor. A first contact on the first contact-diffusion-layer has a shape with a diameter in the channel-width direction larger than that in the channel-length direction when viewed from above the substrate. A second contact on the second contact-diffusion-layer has a shape with a diameter in the channel-width direction smaller than that of the first contact and a diameter in the channel-length direction almost equal to that of the first contact when viewed from above the substrate. A wiring is electrically connected to the first transistor through the second contact.
    Type: Grant
    Filed: June 5, 2014
    Date of Patent: May 5, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenichi Abe, Takuya Futatsuyama, Jumpei Sato
  • Patent number: 8994145
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor chip which includes a semiconductor integrated circuit provided in an insulator, a first pad a pad having an upper surface of which is exposed via an opening formed in the insulator, and capacitors provided in a capacitor region of the semiconductor chip under the pad. The capacitors are provided in the capacitor region to satisfy a rule of a coverage. And contacts respectively connected to two electrodes of the capacitors are provided at positions that do not vertically overlap the opening.
    Type: Grant
    Filed: September 18, 2011
    Date of Patent: March 31, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Jumpei Sato
  • Publication number: 20140284810
    Abstract: In a semiconductor device, a first contact-diffusion-layer is in a first well to be connected to the first well and extends in a channel width direction of a first transistor in a first well. A second contact-diffusion-layer is in the first well so as to be electrically connected to the first well and extends in a channel-length direction of the first transistor. A first contact on the first contact-diffusion-layer has a shape with a diameter in the channel-width direction larger than that in the channel-length direction when viewed from above the substrate. A second contact on the second contact-diffusion-layer has a shape with a diameter in the channel-width direction smaller than that of the first contact and a diameter in the channel-length direction almost equal to that of the first contact when viewed from above the substrate. A wiring is electrically connected to the first transistor through the second contact.
    Type: Application
    Filed: June 5, 2014
    Publication date: September 25, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kenichi ABE, Takuya FUTATSUYAMA, Jumpei SATO