Abstract: A semiconductor memory device includes a memory array provided above a substrate in a first direction intersecting a surface of the substrate. A first peripheral circuit is provided between the substrate and the memory array. A second peripheral circuit is provided between the substrate and the memory array and apart from the first peripheral circuit in a second direction parallel to the surface of the substrate. A sense amplifier is provided between the substrate and the memory array and between the first and second peripheral circuits, and a word line switch circuit extending in the second direction is also provided. A length of the second peripheral circuit in the second direction is smaller than half of a length of the sense amplifier in the second direction.

Abstract: In a semiconductor memory device, a first plane includes a first memory cell array provided above a substrate in a first direction. A first power supply circuit is provided between the substrate and the first memory cell array, and a first sense amplifier is provided between the substrate and the first memory cell array. A second plane includes a second memory cell array provided above the substrate and a second power supply circuit provided between the substrate and the second memory cell array. A second sense amplifier is provided between the substrate and the second memory cell array. When viewed in the first direction, the first power supply circuit and the first sense amplifier overlap the first memory cell array, and the second power supply circuit and the second sense amplifier overlap the second memory cell array.

Abstract: According to one embodiment, a semiconductor memory device includes the following structure. A memory array is provided on a first-direction side of a substrate. The first direction intersects the substrate. The first peripheral circuit is provided between the substrate and the memory array. The second peripheral circuit is provided between the substrate and the memory array and on a second-direction side of the first peripheral circuit. The second direction intersects the first direction. The sense amplifier is provided between the substrate and the memory array and between the first and second peripheral circuits. A second-direction length of the second peripheral circuit is smaller than half a second-direction length of the sense amplifier.

Abstract: A semiconductor memory device is provided that includes a plurality of memory blocks, arranged in a second direction, that are spaced from a semiconductor substrate in a first direction intersecting with a surface of the semiconductor substrate; a first wiring that is farther from the semiconductor substrate than the plurality of memory blocks in the first direction; a second wiring that is closer to the semiconductor substrate than the plurality of memory blocks in the first direction; a first contact; a first transistor with a first active region disposed in the semiconductor substrate, the second wiring being electrically connected to a first memory block among the plurality of memory blocks via the first transistor; and a second transistor where the second wiring being electrically connected to a second memory block among the plurality of memory blocks via the second transistor.

Abstract: A semiconductor memory device includes a semiconductor substrate, memory blocks, a first wiring, a second wiring, a first contact, a first transistor, and a second transistor. The memory blocks are spaced from the semiconductor substrate in a first direction and are arranged in a second direction. The first wiring is farther from the semiconductor substrate than the memory blocks. The second wiring is closer to the semiconductor substrate than the memory blocks. The first contact is electrically connected between the first wiring and the second wiring. The first and second transistors are disposed on the semiconductor substrate. The first transistor is electrically connected between the second wiring and a first memory block. The second transistor is electrically connected between the second wiring and a second memory block. The first contact is disposed between the first transistor and the second transistor in the second direction.

Abstract: According to one embodiment, a semiconductor memory device includes the following structure. A memory array is provided on a first-direction side of a substrate. The first direction intersects the substrate. The first peripheral circuit is provided between the substrate and the memory array. The second peripheral circuit is provided between the substrate and the memory array and on a second-direction side of the first peripheral circuit. The second direction intersects the first direction. The sense amplifier is provided between the substrate and the memory array and between the first and second peripheral circuits. A second-direction length of the second peripheral circuit is smaller than half a second-direction length of the sense amplifier.

Abstract: A solar cell element is provided with a semiconductor substrate, a passivation layer, and an electrode. The semiconductor substrate has a first surface and a second surface that is positioned on a back side of the first surface. The passivation layer is positioned on the second surface of the semiconductor substrate. The electrode is positioned on the passivation layer and positioned in the state of being electrically connected to the semiconductor substrate. The electrode includes a linear electrode part that is positioned along a peripheral edge of the semiconductor substrate when the semiconductor substrate is seen from the second surface side in plane perspective view, and is positioned in the state of penetrating the passivation layer in a thickness direction.

Abstract: A semiconductor memory device includes n interconnect layers above a substrate; and a first interconnect region between an end of a control circuit and an end of the substrate in a direction of a first axis beside a first pad region in a direction of a second axis. The n interconnect layers are located at different levels from the substrate. Each of the n interconnect layers includes an interconnect. The first interconnect region includes no transistor, and no contact coupled to the substrate. The first interconnect region includes an interconnect extending along the second axis in m (m is a natural number equal to or larger than 3, larger than n/2, and equal to or smaller than n) interconnect layers of the n interconnect layers.

Abstract: The task is to provide a system which supports smooth patient referral from a referral source medical institution to a referral destination medical institution and which particularly prevents readmission due to cases that are difficult to determine simply based on patient attributes or due to the quality of medical services. To achieve this task, a referral difficult degree calculation unit calculates a referral difficulty degree which quantifies the risk that a patient cannot be discharged because a referral destination cannot be found, in consideration of a readmission risk calculated by a readmission risk calculation unit, the geographical distance between the patient and the referral destination medical institution, the total number of patients accepted, and the number of beds available. This referral difficulty degree is outputted to an output unit of the referral source medical institution or the referral destination medical institution.

Abstract: According to one embodiment, a semiconductor storage device includes: a memory cell array including a plurality of bit lines; a sense amplifier; a first circuit including a plurality of transistors respectively connected to the plurality of bit lines and the sense amplifier; and a plurality of interconnects which are provided at a position higher than the bit lines in the first circuit and are not directly connected to the first circuit. The semiconductor storage device does not include, at a position higher than the plurality of interconnects, an interconnect which electrically connects two positions in the semiconductor storage device.

Abstract: A semiconductor memory device includes n interconnect layers above a substrate; and a first interconnect region between an end of a control circuit and an end of the substrate in a direction of a first axis beside a first pad region in a direction of a second axis. The n interconnect layers are located at different levels from the substrate. Each of the n interconnect layers includes an interconnect. The first interconnect region includes no transistor, and no contact coupled to the substrate. The first interconnect region includes an interconnect extending along the second axis in m (m is a natural number equal to or larger than 3, larger than n/2, and equal to or smaller than n) interconnect layers of the n interconnect layers.

Abstract: A semiconductor memory device includes n interconnect layers above a substrate; and a first interconnect region between an end of a control circuit and an end of the substrate in a direction of a first axis beside a first pad region in a direction of a second axis. The n interconnect layers are located at different levels from the substrate. Each of the n interconnect layers includes an interconnect. The first interconnect region includes no transistor, and no contact coupled to the substrate. The first interconnect region includes an interconnect extending along the second axis in m (m is a natural number equal to or larger than 3, larger than n/2, and equal to or smaller than n) interconnect layers of the n interconnect layers.

Abstract: A semiconductor memory device includes n interconnect layers above a substrate; and a first interconnect region between an end of a control circuit and an end of the substrate in a direction of a first axis beside a first pad region in a direction of a second axis. The n interconnect layers are located at different levels from the substrate. Each of the n interconnect layers includes an interconnect. The first interconnect region includes no transistor, and no contact coupled to the substrate. The first interconnect region includes an interconnect extending along the second axis in m (m is a natural number equal to or larger than 3, larger than n/2, and equal to or smaller than n) interconnect layers of the n interconnect layers.

Abstract: Upon evaluation of a value of a diagnostic process, the value of a diagnostic process is evaluated not based on a simple cost but on a cost required for all processes of a patient who was in the diagnostic process through a follow-up survey. Diagnostic processes that are not relevant to a target diagnostic process are eliminated, clustering is performed on patients to divide the patients into clinically meaningful homogeneous groups, and the target diagnostic process is evaluated for each of the homogeneous groups. For the purpose, importance scores of data pieces of the clinical data are calculated and the relevant data is output using the output result of the medical knowledge extraction unit, clustering is performed on patients in the clinical data, and a clinical index and a cost are output for each of the clusters.

Abstract: A solar cell element is provided with a semiconductor substrate, a passivation layer, and an electrode. The semiconductor substrate has a first surface and a second surface that is positioned on a back side of the first surface. The passivation layer is positioned on the second surface of the semiconductor substrate. The electrode is positioned on the passivation layer and positioned in the state of being electrically connected to the semiconductor substrate. The electrode includes a linear electrode part that is positioned along a peripheral edge of the semiconductor substrate when the semiconductor substrate is seen from the second surface side in plane perspective view, and is positioned in the state of penetrating the passivation layer in a thickness direction.

Abstract: According to one embodiment, a semiconductor storage device includes: a memory cell array including a plurality of bit lines; a sense amplifier; a first circuit including a plurality of transistors respectively connected to the plurality of bit lines and the sense amplifier; and a plurality of interconnects which are provided at a position higher than the bit lines in the first circuit and are not directly connected to the first circuit. The semiconductor storage device does not include, at a position higher than the plurality of interconnects, an interconnect which electrically connects two positions in the semiconductor storage device.

Abstract: An insulating paste includes a siloxane resin and an organic solvent. The siloxane resin includes a phenyl group and an alkyl group expressed by a general formula CnH2n+1, in which n is a natural number. The number of alkyl groups is greater than the number of phenyl groups in the siloxane resin.

Abstract: According to one embodiment, a semiconductor memory device includes a core section, a corner area adjacent section, a first circuit block and a second circuit block, and multiple wiring layers. The corner area adjacent section is arranged adjacently to a corner area positioned in a corner of the core section adjacently to the sense amplifier and the row decoder. The multiple wiring layers are provided in each of the first circuit block and the second circuit block, wherein a first wire in one of the multiple wiring layers in the first circuit block is arranged parallel to a second wire included in a wiring layer in the second circuit block which is the same as the wiring layer of the first wire.

Abstract: According to one embodiment, a semiconductor memory device includes a core section, a corner area adjacent section, a first circuit block and a second circuit block, and multiple wiring layers. The corner area adjacent section is arranged adjacently to a corner area positioned in a corner of the core section adjacently to the sense amplifier and the row decoder. The multiple wiring layers are provided in each of the first circuit block and the second circuit block, wherein a first wire in one of the multiple wiring layers in the first circuit block is arranged parallel to a second wire included in a wiring layer in the second circuit block which is the same as the wiring layer of the first wire.

Abstract: The task is to provide a system which supports smooth patient referral from a referral source medical institution to a referral destination medical institution and which particularly prevents readmission due to cases that are difficult to determine simply based on patient attributes or due to the quality of medical services. To achieve this task, a referral difficult degree calculation unit calculates a referral difficulty degree which quantifies the risk that a patient cannot be discharged because a referral destination cannot be found, in consideration of a readmission risk calculated by a readmission risk calculation unit, the geographical distance between the patient and the referral destination medical institution, the total number of patients accepted, and the number of beds available. This referral difficulty degree is outputted to an output unit of the referral source medical institution or the referral destination medical institution.