Patents by Inventor Jun Iijima

Jun Iijima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190296035
    Abstract: According to an embodiment, a semiconductor memory device includes a substrate, a stacked body, a plurality of columnar portions, a plurality of interconnects, and a plurality of connection portions. The plurality of interconnects extends in a first direction parallel to an upper surface of the substrate. When viewed from a second direction perpendicular to the stacking direction and the first direction, a portion of a first connection portion overlaps a portion of a second connection portion. The first connection portion is connected to a first interconnect of the plurality of interconnects. The second connection portion is connected to a second interconnect of the plurality of interconnects adjacent to the first interconnect in the second direction.
    Type: Application
    Filed: September 11, 2018
    Publication date: September 26, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Jun IIJIMA, Masayoshi Tagami, Takamasa Usui, Takahito Nishimura
  • Publication number: 20190287955
    Abstract: In one embodiment, a semiconductor device includes a first interconnection including a first extending portion extending in a first direction, and a first curved portion curved with respect to the first extending portion. The device further includes a second interconnection including a second extending portion extending in the first direction and adjacent to the first extending portion in a second direction, and a second curved portion curved with respect to the second extending portion. The device further includes a first plug provided on the first curved portion, or on a first non-opposite portion included in the first extending portion and not opposite to the second extending portion in the second direction. The device further includes a second plug provided on the second curved portion, or on a second non-opposite portion included in the second extending portion and not opposite to the first extending portion in the second direction.
    Type: Application
    Filed: September 10, 2018
    Publication date: September 19, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Jun IIJIMA, Yumi NAKAJIMA
  • Patent number: 10381374
    Abstract: According to one embodiment, a semiconductor memory device includes a first memory chip, a circuit chip, and an external connection electrode on a surface of the first memory chip. The first memory chip comprises first conductors stacked via an insulator, and a first pillar passing the first conductors. The circuit chip comprises a substrate, a control circuit, and a second conductor connected to the control circuit, the circuit chip being attached to the first memory chip. The external connection electrode comprises a portion extending from a side of the surface of the first memory chip through the first memory chip and connected to the second conductor. Part of the first conductors is between the external connection electrode and the substrate.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: August 13, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Masayoshi Tagami, Jun Iijima, Ryota Katsumata, Kazuyuki Higashi
  • Patent number: 10331028
    Abstract: According to one embodiment, an imprinting apparatus is provided. The imprinting apparatus includes a controller that controls a resist drop position on a wafer to be imprinted with a pattern, using a first resist drop recipe corresponding to a first topography of the wafer.
    Type: Grant
    Filed: February 1, 2016
    Date of Patent: June 25, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takahito Nishimura, Jun Iijima
  • Publication number: 20190181002
    Abstract: A method for manufacturing a semiconductor device includes forming a SiN film on a substrate. Plasma treatment is applied to the SiN film using a He-containing gas.
    Type: Application
    Filed: December 12, 2017
    Publication date: June 13, 2019
    Applicant: ASM IP Holding B.V.
    Inventors: Toshiaki Iijima, Masaki Tokunaga, Jun Kawahara
  • Patent number: 10308014
    Abstract: A computer program for an information processing device communicating with a droplet discharging device is provided. The droplet discharging device is configured to form rendering data on a printing medium by being moved by a user on the printing medium, and includes a position calculation unit for calculating a position of the droplet discharging device, and a droplet discharging unit for discharging a droplet in accordance with the rendering data and location information. The computer program is configured to cause the information processing device to function as a scanning direction output unit for outputting a scanning direction of the droplet discharging device.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: June 4, 2019
    Assignee: Ricoh Company, Ltd.
    Inventors: Jun Watanabe, Yasunari Harada, Hideaki Iijima, Hiroki Tanaka, Toshiaki Hosokawa, Shunsuke Shitaoka
  • Patent number: 10297578
    Abstract: A memory device includes a first memory cell array, a second memory cell array disposed in a first direction with respect to the first memory cell array, a first contact plug extending in the first direction through the first memory cell array, and a second contact plug extending in the first direction through the second memory cell array. The first memory cell array includes first electrode layers stacked in a first direction, and a first semiconductor pillar extending through the first electrode layers in the first direction. The second memory cell array including second electrode layers stacked in the first direction, and a second semiconductor pillar extending in the first direction through the second electrode layers. The first contact plug is electrically connected to the first semiconductor pillar, and the second contact plug is electrically connected to the second semiconductor pillar and the first contact plug.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: May 21, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Masayoshi Tagami, Ryota Katsumata, Jun Iijima, Tetsuya Shimizu, Takamasa Usui, Genki Fujita
  • Publication number: 20190143674
    Abstract: A droplet discharge apparatus discharges a droplet to form an image on a recording medium while being moved by a user. The droplet discharge apparatus includes a head to discharge a droplet on a recording medium according to image data, a sensor to detect a movement amount of the droplet discharge apparatus in a predetermined period, and a processor. The processor is configured to instruct droplet discharge based on the image data and the movement amount detected by the sensor, determine floating of the droplet discharge apparatus from the recording medium based on information from the sensor, and stop the droplet discharge in response to a determination that the droplet discharge apparatus is floating.
    Type: Application
    Filed: September 19, 2018
    Publication date: May 16, 2019
    Inventors: Hideaki IIJIMA, Tetsuyoshi NAKATA, Jun WATANABE, Yasunari HARADA, Toshiaki HOSOKAWA, Shunsuke SHITAOKA
  • Publication number: 20190088676
    Abstract: According to one embodiment, a semiconductor memory device includes a first memory chip, a circuit chip, and an external connection electrode on a surface of the first memory chip. The first memory chip comprises first conductors stacked via an insulator, and a first pillar passing the first conductors. The circuit chip comprises a substrate, a control circuit, and a second conductor connected to the control circuit, the circuit chip being attached to the first memory chip. The external connection electrode comprises a portion extending from a side of the surface of the first memory chip through the first memory chip and connected to the second conductor. Part of the first conductors is between the external connection electrode and the substrate.
    Type: Application
    Filed: March 5, 2018
    Publication date: March 21, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Masayoshi TAGAMI, Jun IIJIMA, Ryota KATSUMATA, Kazuyuki HIGASHI
  • Publication number: 20180261575
    Abstract: A memory device includes a first memory cell array, a second memory cell array disposed in a first direction with respect to the first memory cell array, a first contact plug extending in the first direction through the first memory cell array, and a second contact plug extending in the first direction through the second memory cell array. The first memory cell array includes first electrode layers stacked in a first direction, and a first semiconductor pillar extending through the first electrode layers in the first direction. The second memory cell array including second electrode layers stacked in the first direction, and a second semiconductor pillar extending in the first direction through the second electrode layers. The first contact plug is electrically connected to the first semiconductor pillar, and the second contact plug is electrically connected to the second semiconductor pillar and the first contact plug.
    Type: Application
    Filed: September 15, 2017
    Publication date: September 13, 2018
    Applicant: Toshiba Memory Corporation
    Inventors: Masayoshi TAGAMI, Ryota Katsumata, Jun Iijima, Tetsuya Shimizu, Takamasa Usui, Genki Fujita
  • Patent number: 10075631
    Abstract: An imaging apparatus which can take shots sequentially by self-timer. The imaging apparatus, in response to input of a user's start operation to perform self-timer shooting, plays back a first voice file including a voice of a predetermined playback time period one time, the first voice file including a voice providing guidance to prepare for shooting, determines whether the first voice file has been played back to completion one time, and performs shooting one time when it is determined that the first voice file has been played back to completion one time, without performing a time-check function. The imaging apparatus repeats playback of the first voice file and performs shooting a predetermined number of times.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: September 11, 2018
    Assignee: CASIO COMPUTER CO., LTD.
    Inventors: Jun Iijima, Junichi Miyasaka
  • Patent number: 9887262
    Abstract: A semiconductor device includes a semiconductor layer and a first insulating film provided on the semiconductor layer. The first insulating film has a surface opposite to the semiconductor layer, the surface including a first portion, a second portion and a third portion between the first portion and the second portion. The device includes a first interconnection provided on a first portion and a second interconnection provided on the second portion. The first interconnection and the second interconnection extend in a first direction. The device further includes a conductor and a nitride layer. The conductor extends through the first insulating film in a second direction from each of the first interconnection and the second interconnection toward the semiconductor layer, and the conductor electrically connects the first interconnection to the semiconductor layer. The nitrided layer is provided at least on the third surface.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: February 6, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Yoshihiro Minami, Jun Iijima, Tetsuya Shimizu, Takamasa Usui, Masayoshi Tagami
  • Patent number: 9723221
    Abstract: An imaging device shoots a common subject in synchronization with other imaging devices. The imaging device includes a processor. The processor receives states of the other imaging devices, compare an own state of the imaging device with the received states of the other imaging devices, and determine whether the imaging device functions as a main device or a subordinate device for setting an imaging condition. When the processor determines that the imaging device functions as the main device, the processor sends imaging information acquired or determined by the imaging device for shooting the common subject to the subordinate devices. When the processor determines that the imaging device functions as the subordinate device, the processor sets the imaging condition in the imaging device based on the imaging information received from the main device.
    Type: Grant
    Filed: August 5, 2015
    Date of Patent: August 1, 2017
    Assignee: CASIO COMPUTER CO., LTD.
    Inventors: Jun Iijima, Kazuya Nara, Kouichi Saitou, Toshiya Kiso, Takuya Yamada
  • Publication number: 20170136683
    Abstract: According to one embodiment, an imprinting apparatus is provided. The imprinting apparatus includes a controller that controls a resist drop position on a wafer to be imprinted with a pattern, using a first resist drop recipe corresponding to a first topography of the wafer.
    Type: Application
    Filed: February 1, 2016
    Publication date: May 18, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takahito NISHIMURA, Jun IIJIMA
  • Patent number: 9589974
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes: an interlayer insulating film; an element separating region separating a semiconductor layer in the memory cell region; a gate electrode provided on one of plurality of semiconductor regions in the memory cell region; a contact electrode having a sidewall in contact with the interlayer insulating film and electrically connected to the one of the plurality of semiconductor regions in the memory cell region; a first wiring layer connected to an upper end of the contact electrode in the memory cell region; and a second wiring layer in a third direction, having an upper end higher than the upper end of the contact electrode, having a lower end lower than the upper end of the contact electrode, and having a sidewall at least partly in contact with the interlayer insulating film in the peripheral region.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: March 7, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Jun Iijima, Yoshiaki Himeno, Takamasa Usui
  • Publication number: 20160247783
    Abstract: A semiconductor device includes a semiconductor layer and a first insulating film provided on the semiconductor layer. The first insulating film has a surface opposite to the semiconductor layer, the surface including a first portion, a second portion and a third portion between the first portion and the second portion. The device includes a first interconnection provided on a first portion and a second interconnection provided on the second portion. The first interconnection and the second interconnection extend in a first direction. The device further includes a conductor and a nitride layer. The conductor extends through the first insulating film in a second direction from each of the first interconnection and the second interconnection toward the semiconductor layer, and the conductor electrically connects the first interconnection to the semiconductor layer. The nitrided layer is provided at least on the third surface.
    Type: Application
    Filed: August 27, 2015
    Publication date: August 25, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yoshihiro MINAMI, Jun IIJIMA, Tetsuya SHIMIZU, Takamasa USUI, Masayoshi TAGAMI
  • Publication number: 20160050357
    Abstract: An imaging device shoots a common subject in synchronization with other imaging devices. The imaging device includes a processor. The processor receives states of the other imaging devices, compare an own state of the imaging device with the received states of the other imaging devices, and determine whether the imaging device functions as a main device or a subordinate device for setting an imaging condition. When the processor determines that the imaging device functions as the main device, the processor sends imaging information acquired or determined by the imaging device for shooting the common subject to the subordinate devices. When the processor determines that the imaging device functions as the subordinate device, the processor sets the imaging condition in the imaging device based on the imaging information received from the main device.
    Type: Application
    Filed: August 5, 2015
    Publication date: February 18, 2016
    Applicant: CASIO COMPUTER CO., LTD.
    Inventors: Jun IIJIMA, Kazuya NARA, Kouichi SAITOU, Toshiya KISO, Takuya YAMADA
  • Publication number: 20150271394
    Abstract: The present invention provides an imaging apparatus which can take shots sequentially by self-timer. The imaging apparatus includes an output unit, an imaging unit, and an imaging control unit. The output unit plays back a first voice file including a voice of a predetermined playback time period for guidance to prepare for shooting. The imaging unit performs shooting one time after playback of the first voice file by the output unit is ended. The imaging control unit repeats playback by the output unit and shooting by the imaging unit a predetermined number of times.
    Type: Application
    Filed: January 30, 2015
    Publication date: September 24, 2015
    Applicant: CASIO COMPUTER CO., LTD.
    Inventors: Jun IIJIMA, Junichi MIYASAKA
  • Publication number: 20150069491
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes: an interlayer insulating film; an element separating region separating a semiconductor layer in the memory cell region; a gate electrode provided on one of plurality of semiconductor regions in the memory cell region; a contact electrode having a sidewall in contact with the interlayer insulating film and electrically connected to the one of the plurality of semiconductor regions in the memory cell region; a first wiring layer connected to an upper end of the contact electrode in the memory cell region; and a second wiring layer in a third direction, having an upper end higher than the upper end of the contact electrode, having a lower end lower than the upper end of the contact electrode, and having a sidewall at least partly in contact with the interlayer insulating film in the peripheral region.
    Type: Application
    Filed: January 24, 2014
    Publication date: March 12, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Jun IIJIMA, Yoshiaki HIMENO, Takamasa USUI
  • Patent number: 8709939
    Abstract: A multilevel interconnect structure in a semiconductor device and methods for fabricating the same are described. The multilevel interconnect structure in the semiconductor device includes a first insulating layer formed on a semiconductor wafer, a Cu interconnect layer formed on the first insulating layer, a second insulating layer formed on the Cu interconnect layer, and a metal oxide layer formed at an interface between the Cu interconnect layer and the second insulating layer. The metal oxide layer is formed by immersion-plating a metal, such as Sn or Zn, on the Cu interconnect layer and then heat-treating the plated layer in an oxidizing atmosphere.
    Type: Grant
    Filed: October 2, 2012
    Date of Patent: April 29, 2014
    Assignees: Semiconductor Technology Academic Research Center, National University Corporation Tohoku University
    Inventors: Junichi Koike, Yoshito Fujii, Jun Iijima, Noriyoshi Shimizu, Kazuyoshi Maekawa, Koji Arita, Ryotaro Yagi, Masaki Yoshimaru