Abstract: According to an embodiment, a semiconductor memory device includes a substrate, a stacked body, a plurality of columnar portions, a plurality of interconnects, and a plurality of connection portions. The plurality of interconnects extends in a first direction parallel to an upper surface of the substrate. When viewed from a second direction perpendicular to the stacking direction and the first direction, a portion of a first connection portion overlaps a portion of a second connection portion. The first connection portion is connected to a first interconnect of the plurality of interconnects. The second connection portion is connected to a second interconnect of the plurality of interconnects adjacent to the first interconnect in the second direction.

Abstract: In one embodiment, a semiconductor device includes a first interconnection including a first extending portion extending in a first direction, and a first curved portion curved with respect to the first extending portion. The device further includes a second interconnection including a second extending portion extending in the first direction and adjacent to the first extending portion in a second direction, and a second curved portion curved with respect to the second extending portion. The device further includes a first plug provided on the first curved portion, or on a first non-opposite portion included in the first extending portion and not opposite to the second extending portion in the second direction. The device further includes a second plug provided on the second curved portion, or on a second non-opposite portion included in the second extending portion and not opposite to the first extending portion in the second direction.

Abstract: According to one embodiment, a semiconductor memory device includes a first memory chip, a circuit chip, and an external connection electrode on a surface of the first memory chip. The first memory chip comprises first conductors stacked via an insulator, and a first pillar passing the first conductors. The circuit chip comprises a substrate, a control circuit, and a second conductor connected to the control circuit, the circuit chip being attached to the first memory chip. The external connection electrode comprises a portion extending from a side of the surface of the first memory chip through the first memory chip and connected to the second conductor. Part of the first conductors is between the external connection electrode and the substrate.

Abstract: According to one embodiment, an imprinting apparatus is provided. The imprinting apparatus includes a controller that controls a resist drop position on a wafer to be imprinted with a pattern, using a first resist drop recipe corresponding to a first topography of the wafer.

Abstract: A method for manufacturing a semiconductor device includes forming a SiN film on a substrate. Plasma treatment is applied to the SiN film using a He-containing gas.

Abstract: A computer program for an information processing device communicating with a droplet discharging device is provided. The droplet discharging device is configured to form rendering data on a printing medium by being moved by a user on the printing medium, and includes a position calculation unit for calculating a position of the droplet discharging device, and a droplet discharging unit for discharging a droplet in accordance with the rendering data and location information. The computer program is configured to cause the information processing device to function as a scanning direction output unit for outputting a scanning direction of the droplet discharging device.

Abstract: A memory device includes a first memory cell array, a second memory cell array disposed in a first direction with respect to the first memory cell array, a first contact plug extending in the first direction through the first memory cell array, and a second contact plug extending in the first direction through the second memory cell array. The first memory cell array includes first electrode layers stacked in a first direction, and a first semiconductor pillar extending through the first electrode layers in the first direction. The second memory cell array including second electrode layers stacked in the first direction, and a second semiconductor pillar extending in the first direction through the second electrode layers. The first contact plug is electrically connected to the first semiconductor pillar, and the second contact plug is electrically connected to the second semiconductor pillar and the first contact plug.

Abstract: A droplet discharge apparatus discharges a droplet to form an image on a recording medium while being moved by a user. The droplet discharge apparatus includes a head to discharge a droplet on a recording medium according to image data, a sensor to detect a movement amount of the droplet discharge apparatus in a predetermined period, and a processor. The processor is configured to instruct droplet discharge based on the image data and the movement amount detected by the sensor, determine floating of the droplet discharge apparatus from the recording medium based on information from the sensor, and stop the droplet discharge in response to a determination that the droplet discharge apparatus is floating.

Abstract: According to one embodiment, a semiconductor memory device includes a first memory chip, a circuit chip, and an external connection electrode on a surface of the first memory chip. The first memory chip comprises first conductors stacked via an insulator, and a first pillar passing the first conductors. The circuit chip comprises a substrate, a control circuit, and a second conductor connected to the control circuit, the circuit chip being attached to the first memory chip. The external connection electrode comprises a portion extending from a side of the surface of the first memory chip through the first memory chip and connected to the second conductor. Part of the first conductors is between the external connection electrode and the substrate.

Abstract: A memory device includes a first memory cell array, a second memory cell array disposed in a first direction with respect to the first memory cell array, a first contact plug extending in the first direction through the first memory cell array, and a second contact plug extending in the first direction through the second memory cell array. The first memory cell array includes first electrode layers stacked in a first direction, and a first semiconductor pillar extending through the first electrode layers in the first direction. The second memory cell array including second electrode layers stacked in the first direction, and a second semiconductor pillar extending in the first direction through the second electrode layers. The first contact plug is electrically connected to the first semiconductor pillar, and the second contact plug is electrically connected to the second semiconductor pillar and the first contact plug.

Abstract: An imaging apparatus which can take shots sequentially by self-timer. The imaging apparatus, in response to input of a user's start operation to perform self-timer shooting, plays back a first voice file including a voice of a predetermined playback time period one time, the first voice file including a voice providing guidance to prepare for shooting, determines whether the first voice file has been played back to completion one time, and performs shooting one time when it is determined that the first voice file has been played back to completion one time, without performing a time-check function. The imaging apparatus repeats playback of the first voice file and performs shooting a predetermined number of times.

Abstract: A semiconductor device includes a semiconductor layer and a first insulating film provided on the semiconductor layer. The first insulating film has a surface opposite to the semiconductor layer, the surface including a first portion, a second portion and a third portion between the first portion and the second portion. The device includes a first interconnection provided on a first portion and a second interconnection provided on the second portion. The first interconnection and the second interconnection extend in a first direction. The device further includes a conductor and a nitride layer. The conductor extends through the first insulating film in a second direction from each of the first interconnection and the second interconnection toward the semiconductor layer, and the conductor electrically connects the first interconnection to the semiconductor layer. The nitrided layer is provided at least on the third surface.

Abstract: An imaging device shoots a common subject in synchronization with other imaging devices. The imaging device includes a processor. The processor receives states of the other imaging devices, compare an own state of the imaging device with the received states of the other imaging devices, and determine whether the imaging device functions as a main device or a subordinate device for setting an imaging condition. When the processor determines that the imaging device functions as the main device, the processor sends imaging information acquired or determined by the imaging device for shooting the common subject to the subordinate devices. When the processor determines that the imaging device functions as the subordinate device, the processor sets the imaging condition in the imaging device based on the imaging information received from the main device.

Abstract: According to one embodiment, an imprinting apparatus is provided. The imprinting apparatus includes a controller that controls a resist drop position on a wafer to be imprinted with a pattern, using a first resist drop recipe corresponding to a first topography of the wafer.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes: an interlayer insulating film; an element separating region separating a semiconductor layer in the memory cell region; a gate electrode provided on one of plurality of semiconductor regions in the memory cell region; a contact electrode having a sidewall in contact with the interlayer insulating film and electrically connected to the one of the plurality of semiconductor regions in the memory cell region; a first wiring layer connected to an upper end of the contact electrode in the memory cell region; and a second wiring layer in a third direction, having an upper end higher than the upper end of the contact electrode, having a lower end lower than the upper end of the contact electrode, and having a sidewall at least partly in contact with the interlayer insulating film in the peripheral region.

Abstract: A semiconductor device includes a semiconductor layer and a first insulating film provided on the semiconductor layer. The first insulating film has a surface opposite to the semiconductor layer, the surface including a first portion, a second portion and a third portion between the first portion and the second portion. The device includes a first interconnection provided on a first portion and a second interconnection provided on the second portion. The first interconnection and the second interconnection extend in a first direction. The device further includes a conductor and a nitride layer. The conductor extends through the first insulating film in a second direction from each of the first interconnection and the second interconnection toward the semiconductor layer, and the conductor electrically connects the first interconnection to the semiconductor layer. The nitrided layer is provided at least on the third surface.

Abstract: An imaging device shoots a common subject in synchronization with other imaging devices. The imaging device includes a processor. The processor receives states of the other imaging devices, compare an own state of the imaging device with the received states of the other imaging devices, and determine whether the imaging device functions as a main device or a subordinate device for setting an imaging condition. When the processor determines that the imaging device functions as the main device, the processor sends imaging information acquired or determined by the imaging device for shooting the common subject to the subordinate devices. When the processor determines that the imaging device functions as the subordinate device, the processor sets the imaging condition in the imaging device based on the imaging information received from the main device.

Abstract: The present invention provides an imaging apparatus which can take shots sequentially by self-timer. The imaging apparatus includes an output unit, an imaging unit, and an imaging control unit. The output unit plays back a first voice file including a voice of a predetermined playback time period for guidance to prepare for shooting. The imaging unit performs shooting one time after playback of the first voice file by the output unit is ended. The imaging control unit repeats playback by the output unit and shooting by the imaging unit a predetermined number of times.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes: an interlayer insulating film; an element separating region separating a semiconductor layer in the memory cell region; a gate electrode provided on one of plurality of semiconductor regions in the memory cell region; a contact electrode having a sidewall in contact with the interlayer insulating film and electrically connected to the one of the plurality of semiconductor regions in the memory cell region; a first wiring layer connected to an upper end of the contact electrode in the memory cell region; and a second wiring layer in a third direction, having an upper end higher than the upper end of the contact electrode, having a lower end lower than the upper end of the contact electrode, and having a sidewall at least partly in contact with the interlayer insulating film in the peripheral region.

Abstract: A multilevel interconnect structure in a semiconductor device and methods for fabricating the same are described. The multilevel interconnect structure in the semiconductor device includes a first insulating layer formed on a semiconductor wafer, a Cu interconnect layer formed on the first insulating layer, a second insulating layer formed on the Cu interconnect layer, and a metal oxide layer formed at an interface between the Cu interconnect layer and the second insulating layer. The metal oxide layer is formed by immersion-plating a metal, such as Sn or Zn, on the Cu interconnect layer and then heat-treating the plated layer in an oxidizing atmosphere.