Patents by Inventor Jun-Kyu Lee

Jun-Kyu Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170330839
    Abstract: Disclosed herein are a semiconductor package and a method of manufacturing the same. The semiconductor package according to embodiments of the present disclosure includes a wiring including a plurality of layers including an insulating layer and a wiring layer, a semiconductor chip mounted on the wiring and electrically connected to the wiring layer through a bonding pad, a cover member configured to cover side surfaces of the semiconductor chip and the wiring and be in contact with at least one wiring layer, and an encapsulant configured to seal the cover member.
    Type: Application
    Filed: May 11, 2017
    Publication date: November 16, 2017
    Inventors: Il-Hwan KIM, Jun-Kyu LEE, Min-A YOON, Dong-Hoon OH, Tae-Won KIM
  • Patent number: 9793251
    Abstract: Disclosed herein is a semiconductor package in which a semiconductor chip and a mounting device are packaged together. The semiconductor package includes a semiconductor chip, a mounting block on which a first mounting device is mounted on a substrate that includes a circuit formed thereon, and an interconnection part configured to electrically connect the semiconductor chip to the mounting block.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: October 17, 2017
    Assignee: NEPES CO., LTD.
    Inventors: Jun-Kyu Lee, Yong-Tae Kwon
  • Patent number: 9754892
    Abstract: Disclosed herein is a stacked semiconductor package in which semiconductor chips having various sizes are stacked. In accordance with one aspect of the present disclosure, a stacked semiconductor package includes a first semiconductor chip structure provided with a first semiconductor chip, a first mold layer surrounding the first semiconductor chip, and a first penetration electrode passing through the first mold layer and electrically connected to the first semiconductor chip, and a second semiconductor chip structure vertically stacked on the first semiconductor chip structure and provided with a second semiconductor chip and a second penetration electrode electrically connected to the first penetration electrode, wherein the first semiconductor chip structure may have the same size as the second semiconductor chip structure.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: September 5, 2017
    Assignee: NEPES CO., LTD.
    Inventors: Yong-Tae Kwon, Jun-Kyu Lee
  • Patent number: 9653397
    Abstract: Disclosed herein are a semiconductor package and a method of manufacturing the same, which allows a conductive path to be provided to connect upper and lower portions of the semiconductor package. A semiconductor package according to the present invention includes a semiconductor chip, a substrate including an accommodating portion to accommodate the semiconductor chip, a sealing material configured to mold the semiconductor chip and the substrate to be integrated, a through wiring configured to vertically pass through the substrate, a wiring portion configured to electrically connect the semiconductor chip and one side of the through wiring, and an external connection portion to electrically connected to the other side of the through wiring and configured to be able to be electrically connected to an outside, wherein a wiring layer of the wiring portion is provided to be connected to the through wiring.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: May 16, 2017
    Assignee: NEPES CO., LTD.
    Inventors: Yong-Tae Kwon, Jun-Kyu Lee
  • Publication number: 20170069564
    Abstract: Disclosed herein is a wire-bonding type semiconductor package in which a fan out metal pattern is formed and a method of manufacturing the same. The semiconductor package includes a frame configured to transfer an electrical signal between upper and lower parts and having a through part formed therein, a first semiconductor chip accommodated in the through part, a first encapsulant with which the frame and the first semiconductor chip are integrally molded, a second semiconductor chip stacked on the first semiconductor chip, a wire configured to electrically connect the second semiconductor chip to a signal unit of the frame, a second encapsulant with which the second semiconductor chip and the wire are integrally molded, and a wiring unit provided below the frame and the first semiconductor chip and electrically connected to the frame and the first semiconductor chip.
    Type: Application
    Filed: September 2, 2016
    Publication date: March 9, 2017
    Inventors: Yong-Tae KWON, Jun-Kyu LEE
  • Publication number: 20160352119
    Abstract: Provided herein is a charger with improved radiation function capable of lowering its surface temperature to prevent the surface temperature from increasing excessively, the charger according to one aspect of the present disclosure including a printed circuit board on which circuit elements are mounted; an inner case formed in a hollow case shape of which both surfaces are open, and where the printed circuit board is arranged inside; a radiation member formed to cover an outer surface of the inner case to release heat generated in the circuit elements of the printed circuit board; an outer case formed to encompass the radiation member and provided with one open surface; a cover assembled in the outer case and configured to close the one open surface of the outer case; and a terminal coupled to one surface of the outer case, and configured to enable electricity to be supplied to the charger when inserted into a consent.
    Type: Application
    Filed: May 31, 2016
    Publication date: December 1, 2016
    Applicant: SOLUM CO., LTD.
    Inventors: Young-seung NOH, Hyun-su KIM, Soon-joung YIO, Young-joo KIM, Jun-kyu LEE
  • Publication number: 20160293580
    Abstract: Disclosed herein is a system in package and a method of manufacturing the same. The system in package includes a first semiconductor die including a plurality of bond pads, a lead frame disposed around the first semiconductor die and provided with a plurality of signal leads, a second semiconductor die disposed in an upper side of the first semiconductor die and connected to the lead frame by wire bonding, and a fan out metal pattern disposed in a lower side of the first semiconductor die and the lead frame to connect the bond pads and the signal leads electrically and provided with a plurality of metal pads.
    Type: Application
    Filed: November 24, 2015
    Publication date: October 6, 2016
    Applicant: NEPES CO., LTD.
    Inventors: Jun-Kyu LEE, Yong-Tae KWON
  • Publication number: 20160190108
    Abstract: Disclosed herein is a semiconductor package in which a semiconductor chip and a mounting device are packaged together. The semiconductor package includes a semiconductor chip, a mounting block on which a first mounting device is mounted on a substrate that includes a circuit formed thereon, and an interconnection part configured to electrically connect the semiconductor chip to the mounting block.
    Type: Application
    Filed: November 30, 2015
    Publication date: June 30, 2016
    Applicant: NEPES CO., LTD.
    Inventors: Jun-Kyu Lee, Yong-Tae Kwon
  • Publication number: 20160099210
    Abstract: Disclosed herein are a semiconductor package and a method of manufacturing the same, which allows a conductive path to be provided to connect upper and lower portions of the semiconductor package. A semiconductor package according to the present invention includes a semiconductor chip, a substrate including an accommodating portion to accommodate the semiconductor chip, a sealing material configured to mold the semiconductor chip and the substrate to be integrated, a through wiring configured to vertically pass through the substrate, a wiring portion configured to electrically connect the semiconductor chip and one side of the through wiring, and an external connection portion to electrically connected to the other side of the through wiring and configured to be able to be electrically connected to an outside, wherein a wiring layer of the wiring portion is provided to be connected to the through wiring.
    Type: Application
    Filed: September 25, 2015
    Publication date: April 7, 2016
    Applicant: NEPES CO., LTD.
    Inventors: Yong-Tae KWON, Jun-Kyu LEE
  • Publication number: 20150266095
    Abstract: In a method of manufacturing metal powders in a continuous type, metal is heated at a temperature greater than a melting point to form a liquid phase metal, and the liquid phase metal and an emulsion carrier, which is emulsified without reacting with the liquid phase metal, are supplied into a container, and the liquid phase metal and the emulsion carrier are emulsified through Taylor flow to form an emulsion solution. The emulsion solution is discharged from the container, and then, the emulsion solution is cooled at a temperature smaller than the melting point to selectively solidifying the liquid phase metal in the emulsion solution to form the metal powders.
    Type: Application
    Filed: March 17, 2015
    Publication date: September 24, 2015
    Inventors: Woo Young YOON, Jun Kyu LEE, Sung Man CHO
  • Publication number: 20150137346
    Abstract: Disclosed herein is a stacked semiconductor package in which semiconductor chips having various sizes are stacked. In accordance with one aspect of the present disclosure, a stacked semiconductor package includes a first semiconductor chip structure provided with a first semiconductor chip, a first mold layer surrounding the first semiconductor chip, and a first penetration electrode passing through the first mold layer and electrically connected to the first semiconductor chip, and a second semiconductor chip structure vertically stacked on the first semiconductor chip structure and provided with a second semiconductor chip and a second penetration electrode electrically connected to the first penetration electrode, wherein the first semiconductor chip structure may have the same size as the second semiconductor chip structure.
    Type: Application
    Filed: December 28, 2012
    Publication date: May 21, 2015
    Applicant: NEPES CO., LTD.
    Inventors: Yong-Tae Kwon, Jun-Kyu Lee
  • Publication number: 20130334909
    Abstract: Disclosed is a motor, the motor according to a first exemplary embodiment of the present disclosure including a housing, a stator mounted on the housing and including a stator core having a plurality of teeth, an insulator and a coil, a rotor rotatably installed at a center of the stator by a rotation shaft, and an insulation member wrapping an entire surface except for a surface opposite to the rotor of the stator, wherein the insulation member is arranged therein with an insulator and a coil.
    Type: Application
    Filed: June 13, 2013
    Publication date: December 19, 2013
    Inventors: JAE HYUN PARK, JAE JUN EOM, JUN KYU LEE, JA YOUNG SEO
  • Patent number: 8237276
    Abstract: There is provided a bump structure for a semiconductor device, comprising a metal post formed on and electrically connected to an electrode pad on a substrate, a solder post formed on the top surface of the metal post, said solder post having the same horizontal width as the metal post and the top surface of the solder post being substantially rounded, and an intermetallic compound layer disposed at the interface between the metal post and the solder post. An oxide layer formed on the solder post prevents solder post under reflow from being changed into a spherical shape. An intermetallic compound layer may be formed by an aging process at the interface between the metal post and the solder post. The bump structure can realize fine pitch semiconductor package without a short between neighboring bumps.
    Type: Grant
    Filed: July 7, 2010
    Date of Patent: August 7, 2012
    Assignee: NEPES Corporation
    Inventors: Chi Jung Song, In Soo Kang, Gi Jo Jung, Yun Mook Park, Eung Ju Lee, Jun Kyu Lee, Jung Won Lee
  • Publication number: 20110285015
    Abstract: There is provided a bump structure for a semiconductor device, comprising a metal post formed on and electrically connected to an electrode pad on a substrate, a solder post formed on the top surface of the metal post, said solder post having the same horizontal width as the metal post and the top surface of the solder post being substantially rounded, and an intermetallic compound layer disposed at the interface between the metal post and the solder post. An oxide layer formed on the solder post prevents solder post under reflow from being changed into a spherical shape. An intermetallic compound layer may be formed by an aging process at the interface between the metal post and the solder post. The bump structure can realize fine pitch semiconductor package without a short between neighboring bumps.
    Type: Application
    Filed: July 7, 2010
    Publication date: November 24, 2011
    Applicant: NEPES CORPORATION
    Inventors: Chi Jung Song, In Soo Kang, Gi Jo Jung, Yun Mook Park, Eung Ju Lee, Jun Kyu Lee, Jung Won Lee
  • Publication number: 20110195538
    Abstract: The present invention provides a method of fabricating a light emitting diode chip having an active layer between an N type semiconductor layer and a P type semiconductor layer. The method comprises the steps of preparing a substrate; laminating the semiconductor layers on the substrate, the semiconductor layers having the active layer between the N type semiconductor layer and the P type semiconductor layer; and forming grooves on the semiconductor layers laminated on the substrate until the substrate is exposed, whereby inclined sidewalls are formed by the grooves in the semiconductor layers divided into a plurality of chips. According to embodiments of the present invention, a sidewall of a semiconductor layer formed on a substrate of a light emitting diode chip is inclined with respect to the substrate, whereby its directional angle is widened as compared with a light emitting diode chip without such inclination.
    Type: Application
    Filed: April 19, 2011
    Publication date: August 11, 2011
    Applicant: SEOUL OPTO DEVICE CO., LTD.
    Inventors: Jun Hee LEE, Jong Kyu KIM, Yeo Jin YOON
  • Patent number: 7736042
    Abstract: Provided is a back light unit. The back light unit includes a light guide plate having a light guide pattern part; at least one light emitting unit provided at a sidewall of the light guide plate, and irradiating light to the light guide plate; a keypad positioned over the light guide plate, and comprising a resin layer, a base resin layer, a character opening part having a character shape, a key assembly provided at one side, and a key adherence film provided on an upper surface of the base resin layer; and a printed circuit board comprising a metal dome switch positioned under a lower surface of the light guide plate.
    Type: Grant
    Filed: February 20, 2007
    Date of Patent: June 15, 2010
    Assignee: LS Tech Co., Ltd.
    Inventors: Deuk II Park, Choong Yop Rhew, Ki Yong Balk, Young Jin Hyun, Jun Kyu Lee, Hyun Jung Cho, Kyu Jin Choi
  • Patent number: 7416758
    Abstract: A slit coater including buffer members having elasticity and installed at both sides of a slit nozzle unit, compensating for a height difference between both sides, preventing breakdown due to excessive stress generated by the height, and reducing set-up time. The slit coater includes: a table on which an object to be processed is mounted; a slit nozzle unit formed above the table for applying coating solution onto the object; a driving unit moving the slit nozzle unit in a predetermined direction; and buffer members having elasticity installed at both sides of the slit nozzle unit.
    Type: Grant
    Filed: August 19, 2005
    Date of Patent: August 26, 2008
    Assignee: LG Display Co., Ltd.
    Inventors: Jeong Kweon Park, Jun Kyu Lee, Tai Hyun Lim, Seong Kwon
  • Publication number: 20080019115
    Abstract: Provided is a back light unit. The back light unit includes a light guide plate having a light guide pattern part; at least one light emitting unit provided at a sidewall of the light guide plate, and irradiating light to the light guide plate; a keypad positioned over the light guide plate, and comprising a resin layer, a base resin layer, a character opening part having a character shape, a key assembly provided at one side, and a key adherence film provided on an upper surface of the base resin layer; and a printed circuit board comprising a metal dome switch positioned under a lower surface of the light guide plate.
    Type: Application
    Filed: February 20, 2007
    Publication date: January 24, 2008
    Inventors: Deuk II Park, Choong Yop Rhew, Ki Yong Balk, Young Jin Hyun, Jun Kyu Lee, Hyun Jung Cho, Kyu Jin Choi
  • Patent number: 6447823
    Abstract: Yogurt containing encapsulated lactic acid bacteria wherein the lactic acid bacteria 1 is encapsulated within acid resistant and intestine-soluble capsules, and wherein the specific gravity of the liquid yogurt is the same or substantially the same as the specific gravity of the lactic acid bacteria containing capsules whereby the capsules are uniformly distributed in the liquid yogurt.
    Type: Grant
    Filed: October 13, 1998
    Date of Patent: September 10, 2002
    Assignee: Bing-Grae Co., Ltd.
    Inventors: Young-Sup Shin, Byung-Hak Baik, Jun-Kyu Lee
  • Patent number: 5901716
    Abstract: A wafer cleaning apparatus includes at least one nozzle fixing tube disposed in a wall of a cleaning bath. A plurality of injection nozzles are arranged on the nozzle fixing tube for spraying a compressed cleaning solution toward the wafer. A rotating device rotates the at least one nozzle fixing tube and the plurality of injection nozzles within a predetermined angle.
    Type: Grant
    Filed: December 18, 1996
    Date of Patent: May 11, 1999
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung-Seuk Hwang, Jun-Kyu Lee