Patents by Inventor Jun-Wei Chen
Jun-Wei Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7994578Abstract: An Electro-Static Discharge (ESD) protection device is formed in an isolated region of a semiconductor substrate. The ESD protection device may be in the form of a MOS or bipolar transistor or a diode. The isolation structure may include a deep implanted floor layer and one or more implanted wells that laterally surround the isolated region. The isolation structure and ESD protection devices are fabricated using a modular process that includes virtually no thermal processing. Since the ESD device is isolated, two or more ESD devices may be electrically “stacked” on one another such that the trigger voltages of the devices are added together to achieve a higher effective trigger voltage.Type: GrantFiled: September 30, 2008Date of Patent: August 9, 2011Assignees: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong)Inventors: Donald Ray Disney, Jun-Wei Chen, Richard K. Williams, HyungSik Ryu, Wai Tien Chan
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Patent number: 7956437Abstract: A variety of isolation structures for semiconductor substrates include a trench formed in the substrate that is filled with a dielectric material or filled with a conductive material and lined with a dielectric layer along the walls of the trench. The trench may be used in combination with doped sidewall isolation regions. Both the trench and the sidewall isolation regions may be annular and enclose an isolated pocket of the substrate. The isolation structures are formed by modular implant and etch processes that do not include significant thermal processing or diffusion of dopants so that the resulting structures are compact and may be tightly packed in the surface of the substrate.Type: GrantFiled: May 28, 2009Date of Patent: June 7, 2011Assignees: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) LimitedInventors: Richard K. Williams, Donald Ray Disney, Jun-Wei Chen, Wai Tien Chan, HyungSik Ryu
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Patent number: 7812393Abstract: All low-temperature processes are used to fabricate a variety of semiconductor devices in a substrate the does not include an epitaxial layer. The devices include a non-isolated lateral DMOS, a non-isolated extended drain or drifted MOS device, a lateral trench DMOS, an isolated lateral DMOS, JFET and depletion-mode devices, and P-N diode clamps and rectifiers and junction terminations. Since the processes eliminate the need for high temperature processing and employ “as-implanted” dopant profiles, they constitute a modular architecture which allows devices to be added or omitted to the IC without the necessity of altering the processes used to produce the remaining devices.Type: GrantFiled: November 5, 2007Date of Patent: October 12, 2010Assignee: Advanced Analogic Technologies, Inc.Inventors: Richard K. Williams, Donald Ray Disney, Jun-Wei Chen, Wai Tien Chan, HyungSik Ryu
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Patent number: 7738224Abstract: An Electro-Static Discharge (ESD) protection device is formed in an isolated region of a semiconductor substrate. The ESD protection device may be in the form of a MOS or bipolar transistor or a diode. The isolation structure may include a deep implanted floor layer and one or more implanted wells that laterally surround the isolated region. The isolation structure and ESD protection devices are fabricated using a modular process that includes virtually no thermal processing. Since the ESD device is isolated, two or more ESD devices may be electrically “stacked” on one another such that the trigger voltages of the devices are added together to achieve a higher effective trigger voltage.Type: GrantFiled: September 30, 2008Date of Patent: June 15, 2010Assignees: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) LimitedInventors: Donald Ray Disney, Jun-Wei Chen, Richard K. Williams, HyungSik Ryu, Wai Tien Chan
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Patent number: 7719054Abstract: All low-temperature processes are used to fabricate a variety of semiconductor devices in a substrate the does not include an epitaxial layer. The devices include a non-isolated lateral DMOS, a non-isolated extended drain or drifted MOS device, a lateral trench DMOS, an isolated lateral DMOS, JFET and depletion-mode devices, and P-N diode clamps and rectifiers and junction terminations. Since the processes eliminate the need for high temperature processing and employ “as-implanted” dopant profiles, they constitute a modular architecture which allows devices to be added or omitted to the IC without the necessity of altering the processes used to produce the remaining devices.Type: GrantFiled: May 31, 2006Date of Patent: May 18, 2010Assignees: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) LimitedInventors: Richard K. Williams, Donald Ray Disney, Jun-Wei Chen, Wai Tien Chan, HyungSik Ryu
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Patent number: 7626243Abstract: An Electro-Static Discharge (ESD) protection device is formed in an isolated region of a semiconductor substrate. The ESD protection device may be in the form of a MOS or bipolar transistor or a diode. The isolation structure may include a deep implanted floor layer and one or more implanted wells that laterally surround the isolated region. The isolation structure and ESD protection devices are fabricated using a modular process that includes virtually no thermal processing. Since the ESD device is isolated, two or more ESD devices may be electrically “stacked” on one another such that the trigger voltages of the devices are added together to achieve a higher effective trigger voltage.Type: GrantFiled: August 4, 2006Date of Patent: December 1, 2009Assignees: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) LimitedInventors: Donald Ray Disney, Jun-Wei Chen, Richard K. Williams, HyungSik Ryu, Wai Tien Chan
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Publication number: 20090236683Abstract: A variety of isolation structures for semiconductor substrates include a trench formed in the substrate that is filled with a dielectric material or filled with a conductive material and lined with a dielectric layer along the walls of the trench. The trench may be used in combination with doped sidewall isolation regions. Both the trench and the sidewall isolation regions may be annular and enclose an isolated pocket of the substrate. The isolation structures are formed by modular implant and etch processes that do not include significant thermal processing or diffusion of dopants so that the resulting structures are compact and may be tightly packed in the surface of the substrate.Type: ApplicationFiled: May 28, 2009Publication date: September 24, 2009Applicants: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) LimitedInventors: Richard K. Williams, Donald Ray Disney, Wai Tien Chan, Jun-Wei Chen, HyungSik Ryu
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Publication number: 20090034136Abstract: An Electro-Static Discharge (ESD) protection device is formed in an isolated region of a semiconductor substrate. The ESD protection device may be in the form of a MOS or bipolar transistor or a diode. The isolation structure may include a deep implanted floor layer and one or more implanted wells that laterally surround the isolated region. The isolation structure and ESD protection devices are fabricated using a modular process that includes virtually no thermal processing. Since the ESD device is isolated, two or more ESD devices may be electrically “stacked” on one another such that the trigger voltages of the devices are added together to achieve a higher effective trigger voltage.Type: ApplicationFiled: September 30, 2008Publication date: February 5, 2009Applicants: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) LimitedInventors: Donald Ray Disney, Jun-Wei Chen, Richard K. Williams, HyungSik Ryu, Wai Tien Chan
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Publication number: 20090032876Abstract: An Electro-Static Discharge (ESD) protection device is formed in an isolated region of a semiconductor substrate. The ESD protection device may be in the form of a MOS or bipolar transistor or a diode. The isolation structure may include a deep implanted floor layer and one or more implanted wells that laterally surround the isolated region. The isolation structure and ESD protection devices are fabricated using a modular process that includes virtually no thermal processing. Since the ESD device is isolated, two or more ESD devices may be electrically “stacked” on one another such that the trigger voltages of the devices are added together to achieve a higher effective trigger voltage.Type: ApplicationFiled: September 30, 2008Publication date: February 5, 2009Applicants: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) LimitedInventors: Donald Ray Disney, Jun-Wei Chen, Richard K. Williams, HyungSik Ryu, Wai Tien Chan
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Publication number: 20090034137Abstract: An Electro-Static Discharge (ESD) protection device is formed in an isolated region of a semiconductor substrate. The ESD protection device may be in the form of a MOS or bipolar transistor or a diode. The isolation structure may include a deep implanted floor layer and one or more implanted wells that laterally surround the isolated region. The isolation structure and ESD protection devices are fabricated using a modular process that includes virtually no thermal processing. Since the ESD device is isolated, two or more ESD devices may be electrically “stacked” on one another such that the trigger voltages of the devices are added together to achieve a higher effective trigger voltage.Type: ApplicationFiled: September 30, 2008Publication date: February 5, 2009Applicants: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) LimitedInventors: Donald Ray Disney, Jun-Wei Chen, Richard K. Williams, HyungSik Ryu, Wai Tien Chan
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Publication number: 20080290451Abstract: A variety of isolation structures for semiconductor substrates include a trench formed in the substrate that is filled with a dielectric material or filled with a conductive material and lined with a dielectric layer along the walls of the trench. The trench may be used in combination with doped sidewall isolation regions. Both the trench and the sidewall isolation regions may be annular and enclose an isolated pocket of the substrate. The isolation structures are formed by modular implant and etch processes that do not include significant thermal processing or diffusion of dopants so that the resulting structures are compact and may be tightly packed in the surface of the substrate.Type: ApplicationFiled: July 30, 2008Publication date: November 27, 2008Applicant: Advanced Analogic Technologies, Inc.Inventors: Richard K. Williams, Donald Ray Disney, Jun-Wei Chen, Wal Tien Chan, HyungSik Ryu
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Publication number: 20080067585Abstract: All low-temperature processes are used to fabricate a variety of semiconductor devices in a substrate the does not include an epitaxial layer. The devices include a non-isolated lateral DMOS, a non-isolated extended drain or drifted MOS device, a lateral trench DMOS, an isolated lateral DMOS, JFET and depletion-mode devices, and P-N diode clamps and rectifiers and junction terminations. Since the processes eliminate the need for high temperature processing and employ “as-implanted” dopant profiles, they constitute a modular architecture which allows devices to be added or omitted to the IC without the necessity of altering the processes used to produce the remaining devices.Type: ApplicationFiled: November 5, 2007Publication date: March 20, 2008Applicants: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) LimitedInventors: Richard Williams, Donald Disney, Jun-Wei Chen, Wai Chan, Hyung Ryu
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Publication number: 20080067588Abstract: All low-temperature processes are used to fabricate a variety of semiconductor devices in a substrate the does not include an epitaxial layer. The devices include a non-isolated lateral DMOS, a non-isolated extended drain or drifted MOS device, a lateral trench DMOS, an isolated lateral DMOS, JFET and depletion-mode devices, and P-N diode clamps and rectifiers and junction terminations. Since the processes eliminate the need for high temperature processing and employ “as-implanted” dopant profiles, they constitute a modular architecture which allows devices to be added or omitted to the IC without the necessity of altering the processes used to produce the remaining devices.Type: ApplicationFiled: November 5, 2007Publication date: March 20, 2008Applicant: Advanced Analogic Technologies, Inc.Inventors: Richard Williams, Donald Disney, Jun-Wei Chen, Wai Chan, HyungSik Ryu
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Publication number: 20080067586Abstract: All low-temperature processes are used to fabricate a variety of semiconductor devices in a substrate the does not include an epitaxial layer. The devices include a non-isolated lateral DMOS, a non-isolated extended drain or drifted MOS device, a lateral trench DMOS, an isolated lateral DMOS, JFET and depletion-mode devices, and P-N diode clamps and rectifiers and junction terminations. Since the processes eliminate the need for high temperature processing and employ “as-implanted” dopant profiles, they constitute a modular architecture which allows devices to be added or omitted to the IC without the necessity of altering the processes used to produce the remaining devices.Type: ApplicationFiled: November 5, 2007Publication date: March 20, 2008Applicant: Advanced Analogic Technologies, Inc.Inventors: Richard Williams, Donald Disney, Jun-Wei Chen, Wai Chan, HyungSik Ryu
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Publication number: 20080042232Abstract: A variety of isolation structures for semiconductor substrates include a trench formed in the substrate that is filled with a dielectric material or filled with a conductive material and lined with a dielectric layer along the walls of the trench. The trench may be used in combination with doped sidewall isolation regions. Both the trench and the sidewall isolation regions may be annular and enclose an isolated pocket of the substrate. The isolation structures are formed by modular implant and etch processes that do not include significant thermal processing or diffusion of dopants so that the resulting structures are compact and may be tightly packed in the surface of the substrate.Type: ApplicationFiled: August 8, 2007Publication date: February 21, 2008Applicants: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) LimitedInventors: Richard Williams, Donald Disney, Wai Chan, Jun-Wei Chen, HyungSik Ryu
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Publication number: 20080029820Abstract: An Electro-Static Discharge (ESD) protection device is formed in an isolated region of a semiconductor substrate. The ESD protection device may be in the form of a MOS or bipolar transistor or a diode. The isolation structure may include a deep implanted floor layer and one or more implanted wells that laterally surround the isolated region. The isolation structure and ESD protection devices are fabricated using a modular process that includes virtually no thermal processing. Since the ESD device is isolated, two or more ESD devices may be electrically “stacked” on one another such that the trigger voltages of the devices are added together to achieve a higher effective trigger voltage.Type: ApplicationFiled: August 4, 2006Publication date: February 7, 2008Applicants: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) LimitedInventors: Donald Ray Disney, Jun-Wei Chen, Richard K. Williams, HyungSik Ryu, Wai Tien Chan
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Publication number: 20070278568Abstract: All low-temperature processes are used to fabricate a variety of semiconductor devices in a substrate the does not include an epitaxial layer. The devices include a non-isolated lateral DMOS, a non-isolated extended drain or drifted MOS device, a lateral trench DMOS, an isolated lateral DMOS, JFET and depletion-mode devices, and P-N diode clamps and rectifiers and junction terminations. Since the processes eliminate the need for high temperature processing and employ “as-implanted” dopant profiles, they constitute a modular architecture which allows devices to be added or omitted to the IC without the necessity of altering the processes used to produce the remaining devices.Type: ApplicationFiled: May 31, 2006Publication date: December 6, 2007Applicants: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) LimitedInventors: Richard K. Williams, Donald Ray Disney, Jun-Wei Chen, Wai Tien Chan, HyungSik Ryu
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Publication number: 20070278612Abstract: A variety of isolation structures for semiconductor substrates include a trench formed in the substrate that is filled with a dielectric material or filled with a conductive material and lined with a dielectric layer along the walls of the trench. The trench may be used in combination with doped sidewall isolation regions. Both the trench and the sidewall isolation regions may be annular and enclose an isolated pocket of the substrate. The isolation structures are formed by modular implant and etch processes that do not include significant thermal processing or diffusion of dopants so that the resulting structures are compact and may be tightly packed in the surface of the substrate.Type: ApplicationFiled: May 31, 2006Publication date: December 6, 2007Applicants: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) LimitedInventors: Richard K. Williams, Donald Ray Disney, Jun-Wei Chen, Wai Tien Chan, HyungSik Ryu
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Patent number: 7216971Abstract: A pair of eyeglasses with lens fastening arrangement includes a frame having two sets of one or more through holes formed on an outer top and/or bottom edge of each of a pair of openings. The through holes communicate with grooves of the openings. A pair of lenses each includes one or more projections formed on an outer top and/or a bottom edge of each lens. The projection is adapted to lockingly engage with the through hole with peripheral edges of the lenses being inserted into the grooves of the openings of the frame when the lenses are firmly fitted in the openings of the frame. Thereby, loosening of the lenses by bending temples of the eyeglasses is substantially impossible.Type: GrantFiled: June 16, 2006Date of Patent: May 15, 2007Inventor: Jun-Wei Chen
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Publication number: 20070043189Abstract: This invention relates to an amphoteric copolymer, and the use of the copolymer to improve the fluidity and fluidity retention of cementitious materials. The chemical structure of the copolymer is as follows: wherein R1 is H or CH3; R2 is a hydrogen atom, or an alkyl group, a cyclic aliphatic group or an aryl group, having 1 to 10 carbon atoms; D is H or COOR3, R3 is a hydrogen atom, or an alkyl group, a cyclic aliphatic group or an aryl group, having 1 to 10 carbon atoms, or a cationic salt group; Z is an O atom or an NH group; A is a —COO group, a —SO3 group or an acid form; a, b, or c is an integer from 1 to 5000; and p and q are integers from 1 to 10.Type: ApplicationFiled: April 19, 2006Publication date: February 22, 2007Inventors: Kung-Chung Hsu, Fu-Ti Jiang, Jun-Wei Chen