Abstract: A flash memory device and a method of testing the flash memory device are provided. The flash memory device may include a memory cell array including a plurality of bit lines, a control unit configured to output estimated data and an input/output buffer unit including a plurality of page buffers. Each of the plurality of page buffers corresponds to one of the plurality of bit lines in the memory cell array and is configured to read test data programmed in at least a first page of a memory cell array, compare the read-out test data with the estimated data to determine whether the corresponding bit line is in a pass or failure state and output a test result signal. A voltage of the test result signal is maintained when test data of a second page of the memory cell array is read if the corresponding bit line in the first page is in a failure state.

Abstract: A plasma display panel (PDP) with improved address voltage margin and reduced noise brightness such as discharge light or background light during an address discharge. The PDP includes a plurality of barrier ribs between a front substrate and a rear substrate to define a plurality of main discharge spaces and a plurality of auxiliary discharge spaces along a stepped surface of the barrier ribs. The auxiliary discharge spaces provide a shorter discharge path than the main discharge spaces. Address electrodes are provided on the rear substrate for generating address discharges together with the scan electrodes on the front substrate at locations adjacent to the auxiliary discharge spaces. Phosphor layers are respectively formed in the main discharge spaces, and a discharge gas is injected in the main discharge spaces and the auxiliary discharge spaces.

Abstract: A flash memory device includes a memory cell array including a plurality of memory cells; a bit line voltage control signal generator generating and outputting a bit line voltage control signal; and a page buffer unit connected to the memory cell array through a plurality of bit lines, and controlling voltage levels of the plurality of bit lines in response to the bit line voltage control signal output from the bit line voltage control signal generator, wherein the plurality of bit lines comprise a first bit line and a second bit line adjacent to the first bit line, wherein during a bit line pre-charging operation in which the first bit line is in a program inhibited state and the second bit line is in a programming state, the page buffer unit increases a voltage level of the first bit line in response to the bit line voltage control signal, wherein the increase in the voltage level of the first bit line causes a voltage level of the second bit line to increase, and wherein a voltage level of the bit line vol

Abstract: In one embodiment, the non-volatile memory device includes a well of a first conductivity type formed in a substrate, and a first plurality of memory cell transistors connected in series to a bit line formed in the well. A buffer is formed in the substrate outside the well and is connected to the bit line. At least one de-coupling transistor is configured to de-couple the buffer from the bit line, and the de-coupling transistor is formed in the well.

Abstract: In one embodiment, the non-volatile memory device includes a well of a first conductivity type formed in a substrate, and a first plurality of memory cell transistors connected in series to a bit line formed in the well. A buffer is formed in the substrate outside the well and is connected to the bit line. At least one de-coupling transistor is configured to de-couple the buffer from the bit line; and the de-coupling transistor is formed in the well.

Abstract: A plasma display panel (PDP) includes a front substrate and a rear substrate that face each other; a pair of base portions disposed between the front substrate and the rear substrate and are concavely indented in directions away from each other; a pair of barrier walls disposed on the pair of base portions to define a discharge cell; a scan electrode and a sustain electrode that generate a mutual discharge in the discharge cell; an address electrode to cross the scan electrode and that generates an address discharge together with the scan electrode; a phosphor layer disposed in the discharge cell; and a discharge gas injected into the discharge cell.

Abstract: A plasma display panel (PDP) having high efficiency includes a front substrate and a rear substrate facing each other; element portions interposed between the front and rear substrates, and including a first element and a second element disposed in both sides of a main discharge space and a third and a fourth element respectively having a narrow width and protruding on the first element and the second element, wherein the first and second elements, and the third and fourth elements partition stepped spaces along a stepped surface in the main discharge space; sustain electrode pairs alternately disposed on the front substrate, extending along a first direction and causing mutual discharge; dielectric layers which are formed on the front substrate to cover the sustain electrode pairs and in which grooves are formed along a direction that is substantially perpendicular to the first direction; and address electrodes formed on the rear substrate and extending in a second direction that crosses the first direction.

Abstract: In one embodiment, the non-volatile memory device includes a well of a first conductivity type formed in a substrate, and a first plurality of memory cell transistors connected in series to a bit line formed in the well. A buffer is formed in the substrate outside the well and is connected to the bit line. At least one de-coupling transistor is configured to de-couple the buffer from the bit line; and the de-coupling transistor is formed in the well.

Abstract: In one embodiment, the non-volatile memory device includes a well of a first conductivity type formed in a substrate, and a first plurality of memory cell transistors connected in series to a bit line formed in the well. A buffer is formed in the substrate outside the well and is connected to the bit line. At least one de-coupling transistor is configured to de-couple the buffer from the bit line, and the de-coupling transistor is formed in the well.

Abstract: A flash memory device and a method of testing the flash memory device are provided. The flash memory device may include a memory cell array including a plurality of bit lines, a control unit configured to output estimated data and an input/output buffer unit including a plurality of page buffers. Each of the plurality of page buffers corresponds to one of the plurality of bit lines in the memory cell array and is configured to read test data programmed in at least a first page of a memory cell array, compare the read-out test data with the estimated data to determine whether the corresponding bit line is in a pass or failure state and output a test result signal. A voltage of the test result signal is maintained when test data of a second page of the memory cell array is read if the corresponding bit line in the first page is in a failure state.

Abstract: A plasma display panel (PDP) is disclosed. In one embodiment, the PDP includes: i) first and second substrates facing each other, ii) a plurality of first barrier ribs formed between the first and second substrates and configured to define a plurality of discharge cells and iii) a plurality of second barrier ribs dividing each of the discharge cells into a first sub-discharge cell and a second sub-discharge cell, wherein a phosphor layer is formed in the first sub-discharge cells and is not formed in the second sub-discharge cells. According to one embodiment, the PDP has high driving efficiency obtained by improving an address voltage margin, and high image quality obtained by removing noise brightness caused by discharge light resulting from an address discharge, and is suitable for an image display with high efficiency and high resolution.

Abstract: A plasma display panel comprises: first and second substrates facing each other; a plurality of barrier ribs partitioning a discharge space between the first and second substrates so as to define a plurality of discharge cells; address electrodes extending in parallel with each other and in a predetermined direction; first and second electrodes disposed on the second substrate in a direction intersecting the direction of the address electrodes, the first and second electrodes being separated from the address electrodes, the first and second electrodes being provided in correspondence with each of the discharge cells; and phosphor layers coated on the discharge cells. The first and second electrodes protrude in a direction from the second substrate to the first substrate, and face each other so as to provide a space therebetween.

Abstract: A plasma display panel (PDP) with improved address voltage margin and reduced noise brightness such as discharge light or background light during an address discharge. The PDP includes a plurality of barrier ribs between a front substrate and a rear substrate to define a plurality of main discharge spaces and a plurality of auxiliary discharge spaces along a stepped surface of the barrier ribs. The auxiliary discharge spaces provide a shorter discharge path than the main discharge spaces. Address electrodes are provided on the rear substrate for generating address discharges together with the scan electrodes on the front substrate at locations adjacent to the auxiliary discharge spaces. Phosphor layers are respectively formed in the main discharge spaces, and a discharge gas is injected in the main discharge spaces and the auxiliary discharge spaces.

Abstract: A Plasma Display Panel (PDP) has a high aperture ratio of a discharge cell, a high light transmittance, and a high luminous efficiency and a stable and efficient discharge occurs uniformly at a low driving voltage on inner sidewalls of the discharge cell and concentrates in the center of the discharge cell.

Abstract: In one embodiment, the non-volatile memory device includes a well of a first conductivity type formed in a substrate, and a first plurality of memory cell transistors connected in series to a bit line formed in the well. A buffer is formed in the substrate outside the well and is connected to the bit line. At least one de-coupling transistor is configured to de-couple the buffer from the bit line, and the de-coupling transistor is formed in the well.

Abstract: A Plasma Display Panel (PDP) includes: a front panel; a rear panel parallel to and separated from a front panel; a plurality of first barrier ribs of a dielectric, arranged between the front panel and the rear panel, and adapted to define discharge cells together with the front panel and the rear panel; front discharge electrodes and rear discharge electrodes disposed apart to surround each discharge cell within the first barrier ribs, each of the front discharge electrodes and rear discharge electrodes including main line parts and corner parts adapted to connect the adjacent main line parts, wherein inner surfaces of the corner parts facing each discharge cell, are rounded; a phosphor layer arranged in each discharge cell defined by the first barrier ribs; and a discharge gas filling each discharge cell.

Abstract: A plasma display panel comprises: first and second substrates facing each other; a plurality of barrier ribs partitioning a discharge space between the first and second substrates so as to define a plurality of discharge cells; address electrodes extending in parallel with each other and in a predetermined direction; first and second electrodes disposed on the second substrate in a direction intersecting the direction of the address electrodes, the first and second electrodes being separated from the address electrodes, the first and second electrodes being provided in correspondence with each of the discharge cells; and phosphor layers coated on the discharge cells. The first and second electrodes protrude in a direction from the second substrate to the first substrate, and face each other so as to provide a space therebetween.

Abstract: A Plasma Display Panel (PDP) has a high aperture ratio of a discharge cell, a high light transmittance, and a high luminous efficiency and a stable and efficient discharge occurs uniformly at a low driving voltage on inner sidewalls of the discharge cell and concentrates in the center of the discharge cell.

Abstract: A control system for a seatbelt retractor for a seatbelt retractor is to perform the operating performance test of the retractor mounted on a holder structure with at least one sensor and a locking device cooperating therewith throughout a wider range of tilt angle using a PLC, in which the control system includes a motor control portion connected to the PLC to control the rotation of motors at a tilt angle to be inputted in advance; a rotary cylinder control portion for controlling the rotating of a rotary cylinder in order to rotate a spool of the retractor; a stamping control portion for controlling the operating timing of a stamping portion; a memory for enabling various control operations of the PLC; a data register for storing digital data code values corresponding to a plurality of tilt angles; and a multi-axle motion controller for computing the digital data values, therefore enabling the tilt angle of the retractor to be tested with the holder structure being slanted.

Abstract: a control system of a factory automation facility for a seatbelt retractor assembly comprising a factory automation facility and a control portion for controlling the operating of all parts in the factory automation facility, integrally, to enable the mass-production of a seatbelt retractor assembly, in which the factory automation facility comprises a webbing throwing-in portion for throwing-in a webbing of a strip type thereinto by a first webbing supplying portion; first and second webbing position determining devices for guiding the webbing to pass through the hole of a retractor spool, a webbing withdrawing portion including a second webbing supplying portion and a case to withdraw the webbing and store it for a while, first and second part supplying portions for assembling a tongue, a guide ring and a ring mount on the withdrawn webbing, a stopper fixing portion including a third webbing supplying portion for carrying the webbing to a webbing folding portion, upper and lower stopper suppliers for supply