Patents by Inventor Jung Gil Park

Jung Gil Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10930649
    Abstract: An integrated circuit (IC) device includes: a fin-type active area protruding from a substrate and extending in a first horizontal direction; a first nanosheet disposed above an upper surface of the fin-type active area with a first separation space therebetween; a second nanosheet disposed above the first nanosheet with a second separation space therebetween; a gate line extending on the substrate in a second horizontal direction intersecting the first horizontal direction, at least a portion of the gate line being disposed in the second separation space; and a bottom insulation structure disposed in the first separation space.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: February 23, 2021
    Assignee: SAMSUNG ELECTRONICS CO.. LTD.
    Inventors: Myung-gil Kang, Beom-jin Park, Geum-jong Bae, Dong-won Kim, Jung-gil Yang
  • Patent number: 10923476
    Abstract: A semiconductor device includes a first transistor in a first region and a second transistor in a second region. The first transistor includes: a first nanowire, a first gate electrode, a first gate dielectric layer, a first source/drain region, and an inner-insulating spacer. The first nanowire has a first channel region. The first gate electrode surrounds the first nanowire. The first gate dielectric layer is between the first nanowire and the first gate electrode. The first source/drain region is connected to an edge of the first nanowire. The inner-insulating spacer is between the first gate dielectric layer and the first source/drain region. The second transistor includes a second nanowire, a second gate electrode, a second gate dielectric layer, and a second source/drain region. The second nanowire has a second channel region. The second gate electrode surrounds the second nanowire. The second gate dielectric layer is between the second nanowire and the second gate electrode.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: February 16, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Gil Yang, Geum-Jong Bae, Dong-Il Bae, Seung-Min Song, Woo-Seok Park
  • Publication number: 20210028173
    Abstract: A semiconductor device includes a first transistor in a first region of a substrate and a second transistor in a second region of the substrate. The first transistor includes multiple first semiconductor patterns; a first gate electrode; a first gate dielectric layer; a first source/drain region; and an inner-insulating spacer. The second transistor includes multiple second semiconductor patterns; a second gate electrode; a second gate dielectric layer; and a second source/drain region. The second gate dielectric layer extends between the second gate electrode and the second source/drain region and is in contact with the second source/drain region. The first source/drain region is not in contact with the first gate dielectric layer.
    Type: Application
    Filed: September 30, 2020
    Publication date: January 28, 2021
    Inventors: JUNG-GIL YANG, GEUM-JONG BAE, DONG-IL BAE, SEUNG-MIN SONG, WOO-SEOK PARK
  • Patent number: 10877520
    Abstract: An electronic device is disclosed herein, including a first face oriented in a first direction, the first face formed having a curvature and disposed as to be visible from an exterior of the electronic device, a body including a second face oriented towards a second direction opposite to the first direction, the second face visible from the exterior, and a display module visible when viewing the first face, the display module including a flexible display disposed under a window, and the window including a central visible area formed in a substantially rectangular shape including first, second, third and fourth visible areas disposed adjacent to four respective edges of the central visible area.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: December 29, 2020
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Dong Hun Kim, Jung Sik Park, Min Sung Lee, Chung Ha Kim, Joo Ho Seo, Han Gil Song, Seung Ah Oh, So Young Lee, Jung Won Lee, Jong Chul Choi
  • Patent number: 10872983
    Abstract: A semiconductor device includes a substrate, a plurality of channel layers stacked on the substrate, a gate electrode surrounding the plurality of channel layers, and embedded source/drain layers on opposing sides of the gate electrode. The embedded source/drain layers each have a first region and a second region on the first region. The second region has a plurality of layers having different compositions.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: December 22, 2020
    Inventors: Jung Gil Yang, Woo Seok Park, Dong Chan Suh, Seung Min Song, Geum Jong Bae, Dong Il Bae
  • Publication number: 20200381514
    Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate and a gate structure on the substrate. The semiconductor device includes a channel on the substrate. The semiconductor device includes a source/drain layer on the channel. Moreover, the semiconductor device includes a spacer on a sidewall of the gate structure. The spacer includes a central portion overlapping the channel in a vertical direction, and a protrusion portion protruding from the central portion. Related methods of manufacturing semiconductor devices are also provided.
    Type: Application
    Filed: August 18, 2020
    Publication date: December 3, 2020
    Inventors: Seung-Min SONG, Woo-Seok PARK, Jung-Gil YANG, Geum-Jong BAE, Dong-Il Bae
  • Publication number: 20200365602
    Abstract: A semiconductor device includes first and second fin type patterns, first and second gate patterns intersecting the first and second fin type patterns, third and fourth gate patterns intersecting the first fin type pattern between the first and the second gate patterns, a fifth gate pattern intersecting the second fin type pattern, a sixth gate pattern intersecting the second fin type pattern, first to third semiconductor patterns disposed among the first, the third, the fourth and the second gate patterns, and fourth to sixth semiconductor patterns disposed among the first, the fifth, the sixth and the second gate patterns. The first semiconductor pattern to the fourth semiconductor pattern and the sixth semiconductor pattern are electrically connected to a wiring structure, and the fifth semiconductor pattern is not connected to the wiring structure.
    Type: Application
    Filed: December 20, 2019
    Publication date: November 19, 2020
    Inventors: Jung Gil YANG, Sun Wook KIM, Jun Beom PARK, Tae Young KIM, Geum Jong BAE
  • Patent number: 10784344
    Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate and a gate structure on the substrate. The semiconductor device includes a channel on the substrate. The semiconductor device includes a source/drain layer on the channel. Moreover, the semiconductor device includes a spacer on a sidewall of the gate structure. The spacer includes a central portion overlapping the channel in a vertical direction, and a protrusion portion protruding from the central portion. Related methods of manufacturing semiconductor devices are also provided.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: September 22, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Min Song, Woo-Seok Park, Jung-Gil Yang, Geum-Jong Bae, Dong-Il Bae
  • Publication number: 20200283885
    Abstract: The present invention relates to a zirconium alloy cladding with improved oxidation resistance at a high temperature and a method of manufacturing the same. More particularly, the zirconium alloy cladding includes a zirconium alloy cladding; and a Cr—Al thin film coated on the cladding, wherein the thin film is deposited through arc ion plating and the content of Al in the thin film is 5% by weight to 20% by weight.
    Type: Application
    Filed: November 14, 2018
    Publication date: September 10, 2020
    Inventors: Jung Hwan PARK, Hyun Gil KIM, Yang II JUNG, Dong Jun PARK, Byoung Kwon CHOI, Young Ho LEE, Jae Ho YANG
  • Publication number: 20200220006
    Abstract: A semiconductor device includes channels, a gate structure, and a source/drain layer. The channels are disposed at a plurality of levels, respectively, and spaced apart from each other in a vertical direction on an upper surface of a substrate. The gate structure is disposed on the substrate, at least partially surrounds a surface of each of the channels, and extends in a first direction substantially parallel to the upper surface of the substrate. The source/drain layer is disposed at each of opposite sides of the gate structure in a second direction substantially parallel to the upper surface of the substrate and substantially perpendicular to the first direction and is connected to sidewalls of the channels. A length of the gate structure in the second direction changes along the first direction at a first height from the upper surface of the substrate in the vertical direction.
    Type: Application
    Filed: March 12, 2020
    Publication date: July 9, 2020
    Inventors: JUNG-GIL YANG, Beom-Jin Park, Seung-Min Song, Geum-Jong Bae, Dong-Il Bae
  • Patent number: 10693215
    Abstract: An electronic device is provided. The electronic device includes a housing, a communication circuit disposed on one side of the housing, a multi-layered printed circuit board (PCB) disposed on one side of the housing and electrically connected to the communication circuit and an antenna radiator disposed on one side of the housing or defining at least a portion of an outer surface of the housing, and is electrically connected to the communication circuit and the multi-layered printed circuit board, wherein the multi-layered printed circuit board comprises a first conductive pattern disposed in at least one of a plurality of layers thereof to form a capacitance, a second conductive pattern disposed in at least another one of the plurality of layers thereof to form an inductance and a conductive plate disposed between the at least one and the at least other one of the plurality of layers and is electrically isolated from the first conductive pattern and the second conductive pattern.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: June 23, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung Sik Park, Seung Gil Jeon, Jung Su Ha
  • Patent number: 10670799
    Abstract: A backlight unit includes a light guide plate (LGP), a housing that receives the LGP, and a first LGP guide member coupled to the housing. The housing includes a bottom surface, a first sidewall, and a second sidewall. The first and second sidewalls are connected to edges of the bottom surface, are disposed adjacent to each other, and are spaced apart from each other. A first corner of the bottom surface is disposed between the first and second sidewalls, and the first LGP guide member is disposed in a gap between the first and second sidewalls.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: June 2, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Won Chul Lee, Dong Jin Park, Taek Sun Shin, Jin Gyu Sim, Jung Gil Oh, Kwang Sun You, Byoung Jin Jin, Jong Hyeon Choi
  • Patent number: 10665723
    Abstract: A semiconductor device includes a substrate; protruding portions extending in parallel to each other on the substrate; nanowires provided on the protruding portions and separated from each other; gate electrodes provided on the substrate and surrounding the nanowires; source/drain regions provided on the protruding portions and sides of each of the gate electrodes, the source/drain regions being in contact with the nanowires; and first voids provided between the source/drain regions and the protruding portions.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: May 26, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seung Min Song, Woo Seok Park, Geum Jong Bae, Dong Il Bae, Jung Gil Yang
  • Patent number: 10629740
    Abstract: A semiconductor device includes channels, a gate structure, and a source/drain layer. The channels are disposed at a plurality of levels, respectively, and spaced apart from each other in a vertical direction on an upper surface of a substrate. The gate structure is disposed on the substrate, at least partially surrounds a surface of each of the channels, and extends in a first direction substantially parallel to the upper surface of the substrate. The source/drain layer is disposed at each of opposite sides of the gate structure in a second direction substantially parallel to the upper surface of the substrate and substantially perpendicular to the first direction and is connected to sidewalls of the channels. A length of the gate structure in the second direction changes along the first direction at a first height from the upper surface of the substrate in the vertical direction.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: April 21, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-Gil Yang, Beom-Jin Park, Seung-Min Song, Geum-Jong Bae, Dong-Il Bae
  • Publication number: 20200083219
    Abstract: An integrated circuit (IC) device includes: a fin-type active area protruding from a substrate and extending in a first horizontal direction; a first nanosheet disposed above an upper surface of the fin-type active area with a first separation space therebetween; a second nanosheet disposed above the first nanosheet with a second separation space therebetween; a gate line extending on the substrate in a second horizontal direction intersecting the first horizontal direction, at least a portion of the gate line being disposed in the second separation space; and a bottom insulation structure disposed in the first separation space.
    Type: Application
    Filed: March 19, 2019
    Publication date: March 12, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Myung-gil Kang, Beom-jin Park, Geum-jong Bae, Dong-won Kim, Jung-gil Yang
  • Publication number: 20200071566
    Abstract: A slurry composition for a chemical mechanical polishing (CMP) process includes about 0.1% by weight to about 10% by weight of polishing particles, about 0.001% by weight to about 1% by weight of an amine compound, about 0.001% by weight to about 1% by weight of a first cationic compound that is amino acid, about 0.001% by weight to about 1% by weight of a second cationic compound that is organic acid, and about 1% by weight to about 5% by weight of polyhydric alcohol including at least two hydroxyl groups.
    Type: Application
    Filed: August 28, 2019
    Publication date: March 5, 2020
    Applicant: KCTECH CO., LTD.
    Inventors: Sang-hyun Park, Hyo-san Lee, Won-ki Hur, Jung-yoon Kim, Jun-ha Hwang, Chang-gil Kwon, Sung-pyo Lee
  • Publication number: 20190363086
    Abstract: A semiconductor device includes a first transistor in a first region and a second transistor in a second region. The first transistor includes: a first nanowire, a first gate electrode, a first gate dielectric layer, a first source/drain region, and an inner-insulating spacer. The first nanowire has a first channel region. The first gate electrode surrounds the first nanowire. The first gate dielectric layer is between the first nanowire and the first gate electrode. The first source/drain region is connected to an edge of the first nanowire. The inner-insulating spacer is between the first gate dielectric layer and the first source/drain region. The second transistor includes a second nanowire, a second gate electrode, a second gate dielectric layer, and a second source/drain region. The second nanowire has a second channel region. The second gate electrode surrounds the second nanowire. The second gate dielectric layer is between the second nanowire and the second gate electrode.
    Type: Application
    Filed: August 7, 2019
    Publication date: November 28, 2019
    Inventors: JUNG-GIL YANG, GEUM-JONG BAE, DONG-IL BAE, SEUNG-MIN SONG, WOO-SEOK PARK
  • Publication number: 20190323784
    Abstract: A heat transfer fin according to the present disclosure includes a fin body and a plurality of through-holes formed through the fin body and spaced apart from each other in a first direction. When a flow direction of combustion gas that is to flow along a surface of the fin body is referred to as a second direction, the fin body includes a distal surrounding part that surrounds a first distal area located at the farthest upstream side of each of the through-holes. The shortest distance between an inner and an outer boundary of the distal surrounding part that is obtained in an area of the distal surrounding part located at the farthest upstream side is smaller than the shortest distance between the inner and the outer boundary that is obtained in an area of the distal surrounding part located at the farthest downstream side.
    Type: Application
    Filed: April 17, 2019
    Publication date: October 24, 2019
    Inventors: Jun Gil Park, In Chul Jeong, Jung Yul Bae
  • Patent number: 10431585
    Abstract: A semiconductor device includes a first transistor in a first region and a second transistor in a second region. The first transistor includes: a first nanowire, a first gate electrode, a first gate dielectric layer, a first source/drain region, and an inner-insulating spacer. The first nanowire has a first channel region. The first gate electrode surrounds the first nanowire. The first gate dielectric layer is between the first nanowire and the first gate electrode. The first source/drain region is connected to an edge of the first nanowire. The inner-insulating spacer is between the first gate dielectric layer and the first source/drain region. The second transistor includes a second nanowire, a second gate electrode, a second gate dielectric layer, and a second source/drain region. The second nanowire has a second channel region. The second gate electrode surrounds the second nanowire. The second gate dielectric layer is between the second nanowire and the second gate electrode.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: October 1, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Gil Yang, Geum-Jong Bae, Dong-Il Bae, Seung-Min Song, Woo-Seok Park
  • Patent number: 10374286
    Abstract: An electronic device comprising: a housing; a wireless communication transceiver provided within the housing; an antenna radiator provided within the housing; and a cover arranged to cover at least a portion of the antenna radiator and form at least a portion of a surface of the housing, wherein the cover includes a conductive material, and the cover is at least partially detachable from the housing.
    Type: Grant
    Filed: November 19, 2015
    Date of Patent: August 6, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Sik Park, Yeon-Woo Kim, Woo-Sup Lee, Seung-Gil Jeon, Ju-Seok Noh, Jae-Bong Chun, Hyun-Ju Hong