Patents by Inventor JUNG-GUN YOU

JUNG-GUN YOU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200243684
    Abstract: A semiconductor device includes first and second fin patterns on a substrate and extending apart from each other, a field insulating film on the substrate and surrounding parts of the first and second fin patterns, a first gate structure on the first fin pattern and intersecting the first fin pattern, a second gate structure on the second fin pattern and intersecting the second fin pattern, and a separating structure protruding from a top surface of the field insulating film and separating the first and second gate structures, the field insulating film and the separating structure including a same insulating material.
    Type: Application
    Filed: April 14, 2020
    Publication date: July 30, 2020
    Inventors: Jung Gun YOU, Dong Hyun KIM, Byoung-Gi KIM, Yun Suk NAM, Yeong Min JEON, Sung Chul PARK, Dae Won HA
  • Patent number: 10727354
    Abstract: A semiconductor device includes a substrate; a vertical channel structure including a pair of active fins extended in a first direction, perpendicular to an upper surface of the substrate, and an insulating portion interposed between the pair of active fins; an upper source/drain disposed on the vertical channel structure; a lower source/drain disposed below the vertical channel structure and on the substrate; a gate electrode disposed between the upper source/drain and the lower source/drain and surrounding the vertical channel structure; and a gate dielectric layer disposed between the gate electrode and the vertical channel structure. An interval between the gate electrode and the upper source/drain may be smaller than an interval between the gate electrode and the lower source/drain in the first direction.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: July 28, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung Il Park, Jung Gun You, Dong Hun Lee, Yun Il Lee
  • Publication number: 20200220012
    Abstract: A vFET includes a first impurity region doped with first impurities at an upper portion of the substrate. A first diffusion control pattern is formed on the first impurity region. The first diffusion control pattern is configured to control the diffusion of the first impurities. A channel extends in a vertical direction substantially orthogonal to an upper surface of the substrate. A second impurity region is doped with second impurities on the channel. A second diffusion control pattern is between the channel and the second impurity region. The second diffusion control pattern is configured to control the diffusion of the second impurities. A gate structure is adjacent to the channel.
    Type: Application
    Filed: March 12, 2020
    Publication date: July 9, 2020
    Inventors: JUNG-GUN YOU, Chang-Hee KIM, Sung-II PARK, Dong-Hun LEE
  • Publication number: 20200219875
    Abstract: A semiconductor device -is provided. The semiconductor device includes a field insulating film on a substrate, a first fin type pattern which is formed on the substrate and protrudes upward from an upper surface of the field insulating film, and a gate electrode which intersects with the first fin type pattern on the field insulating film and includes a first portion and a second portion, the first portion being located on one side of the first fin type pattern and including a first terminal end of the gate electrode, and the second portion being located on the other side of the first fin type pattern, wherein a height from the substrate to a lowest part of the first portion is different from a height from the substrate to a lowest part of the second portion.
    Type: Application
    Filed: March 17, 2020
    Publication date: July 9, 2020
    Inventors: Jung-Gun You, Se-Wan Park, Baik-Min Sung, Myung-Yoon Um
  • Patent number: 10707348
    Abstract: An integrated circuit device includes a fin-type active area protruding from a substrate; a plurality of liners sequentially covering lower side walls of the fin-type active area; a device isolation layer covering the lower side walls of the fin-type active area with the plurality of liners between the device isolation layer and the fin-type active area; and a gate insulating layer extending to cover a channel region of the fin-type active area, the plurality of liners, and the device isolation layer, and including protrusions located on portions of the gate insulating layer which cover the plurality of liners.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: July 7, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sug-Hyun Sung, Jung-gun You, Gi-gwan Park, Ki-il Kim
  • Patent number: 10692864
    Abstract: Semiconductor devices are provided including a first fin-shaped pattern having first and second sidewalls facing one another and a field insulating film contacting at least a portion of the first fin-shaped pattern. The first fin-shaped pattern includes a lower portion of the first fin-shaped pattern contacting the field insulating film; an upper portion of the first fin-shaped pattern not contacting the field insulating film; a first boundary between the lower portion of the first fin-shaped pattern and the upper portion of the first fin-shaped pattern; and a first fin center line perpendicular to the first boundary and meeting the top of the upper portion of the first fin-shaped pattern. The first sidewall of the upper portion of the first fin-shaped pattern and the second sidewall of the upper portion of the first fin-shaped pattern are asymmetric with respect to the first fin center line.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: June 23, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-Gun You, Se-Wan Park, Baik-Min Sung, Bo-Cheol Jeong
  • Publication number: 20200185382
    Abstract: Semiconductor devices are provided including a first fin-shaped pattern having first and second sidewalls facing one another and a field insulating film contacting at least a portion of the first fin-shaped pattern. The first fin-shaped pattern includes a lower portion of the first fin-shaped pattern contacting the field insulating film; an upper portion of the first fin-shaped pattern not contacting the field insulating film; a first boundary between the lower portion of the first fin-shaped pattern and the upper portion of the first fin-shaped pattern; and a first fin center line perpendicular to the first boundary and meeting the top of the upper portion of the first fin-shaped pattern. The first sidewall of the upper portion of the first fin-shaped pattern and the second sidewall of the upper portion of the first fin-shaped pattern are asymmetric with respect to the first fin center line.
    Type: Application
    Filed: February 18, 2020
    Publication date: June 11, 2020
    Inventors: JUNG-GUN YOU, Se-wan Park, Baik-Min Sung, Bo-Cheol Jeong
  • Publication number: 20200161313
    Abstract: A semiconductor device can include a field insulating film on a substrate and a fin-type pattern of a particular material, on the substrate, having a first sidewall and an opposing second sidewall. The fin-type pattern can include a first portion of the fin-type pattern that protrudes from an upper surface of the field insulating film and a second portion of the fin-type pattern disposed on the first portion. A third portion of the fin-type pattern can be disposed on the second portion where the third portion can be capped by a top rounded surface of the fin-type pattern and the first sidewall can have an undulated profile that spans the first, second and third portions.
    Type: Application
    Filed: January 24, 2020
    Publication date: May 21, 2020
    Inventors: Ki-Il Kim, Jung-Gun You, Gi-Gwan Park
  • Patent number: 10629597
    Abstract: A semiconductor device is provided. The semiconductor device includes a field insulating film on a substrate, a first fin type pattern which is formed on the substrate and protrudes upward from an upper surface of the field insulating film, and a gate electrode which intersects with the first fin type pattern on the field insulating film and includes a first portion and a second portion, the first portion being located on one side of the first fin type pattern and including a first terminal end of the gate electrode, and the second portion being located on the other side of the first fin type pattern, wherein a height from the substrate to a lowest part of the first portion is different from a height from the substrate to a lowest part of the second portion.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: April 21, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-Gun You, Se-Wan Park, Baik-Min Sung, Myung-Yoon Um
  • Patent number: 10629742
    Abstract: A semiconductor device includes first and second fin patterns on a substrate and extending apart from each other, a field insulating film on the substrate and surrounding parts of the first and second fin patterns, a first gate structure on the first fin pattern and intersecting the first fin pattern, a second gate structure on the second fin pattern and intersecting the second fin pattern, and a separating structure protruding from a top surface of the field insulating film and separating the first and second gate structures, the field insulating film and the separating structure including a same insulating material.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: April 21, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung Gun You, Dong Hyun Kim, Byoung-Gi Kim, Yun Suk Nam, Yeong Min Jeon, Sung Chul Park, Dae Won Ha
  • Patent number: 10629729
    Abstract: A vFET includes a first impurity region doped with first impurities at an upper portion of the substrate. A first diffusion control pattern is formed on the first impurity region. The first diffusion control pattern is configured to control the diffusion of the first impurities. A channel extends in a vertical direction substantially orthogonal to an upper surface of the substrate. A second impurity region is doped with second impurities on the channel. A second diffusion control pattern is between the channel and the second impurity region. The second diffusion control pattern is configured to control the diffusion of the second impurities. A gate structure is adjacent to the channel.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: April 21, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-Gun You, Chang-Hee Kim, Sung-Il Park, Dong-Hun Lee
  • Publication number: 20200043807
    Abstract: A method of manufacturing a semiconductor device includes forming a first fin-type pattern and a second fin-type pattern which are separated by a first trench between facing ends thereof, forming a first insulating layer filling the first trench, removing a portion of the first insulating layer to form a second trench on the first insulating layer, and forming a third trench by enlarging a width of the second trench.
    Type: Application
    Filed: October 11, 2019
    Publication date: February 6, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Gi Gwan PARK, Jung Gun YOU, Ki Il KIM, Sug Hyun SUNG, Myung Yoon UM
  • Publication number: 20200027986
    Abstract: An integrated circuit device includes a fin-type active area protruding from a substrate; a plurality of liners sequentially covering lower side walls of the fin-type active area; a device isolation layer covering the lower side walls of the fin-type active area with the plurality of liners between the device isolation layer and the fin-type active area; and a gate insulating layer extending to cover a channel region of the fin-type active area, the plurality of liners, and the device isolation layer, and including protrusions located on portions of the gate insulating layer which cover the plurality of liners.
    Type: Application
    Filed: September 30, 2019
    Publication date: January 23, 2020
    Inventors: Sug-Hyun Sung, Jung-gun YOU, Gi-gwan PARK, Ki-il KIM
  • Patent number: 10522539
    Abstract: Provided is a semiconductor device and a fabricating method thereof. The semiconductor device includes a first trench having a first depth to define a fin, a second trench formed directly adjacent the first trench having a second depth that is greater than the first depth, a field insulation layer filling a portion of the first trench and a portion of the second trench, and a protrusion structure protruding from a bottom of the first trench and being lower than a surface of the field insulation layer.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: December 31, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-Gun You, Sug-Hyun Sung
  • Patent number: 10497804
    Abstract: A vertical transistor structure includes a first transistor and a second transistor. The first transistor includes a first lower electrode connected to a second upper electrode of the second transistor, and a second upper electrode connected to a first lower electrode of the second transistor. The first transistor also includes a gate electrode connected to a gate electrode of the second transistor.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: December 3, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Il Park, Beom-Jin Park, Yun-Il Lee, Jung-Gun You, Dong-Hun Lee
  • Patent number: 10483399
    Abstract: An integrated circuit (IC) device includes a pair of fin-shaped active areas that are adjacent to each other with a fin separation area therebetween, the pair of fin-shaped active areas extend in a line, and a fin separation insulating structure in the fin separation area, wherein the pair of fin-shaped active areas includes a first fin-shaped active area having a first corner defining part of the fin separation area, and wherein the fin separation insulating structure includes a lower insulating pattern that covers sidewalls of the pair of fin-shaped active areas, and an upper insulating pattern on the lower insulating pattern to cover at least part of the first corner, the upper insulating pattern having a top surface at a level higher than a top surface of each of the pair of fin-shaped active areas.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: November 19, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-yup Chung, Myung-yoon Um, Dong-ho Cha, Jung-gun You, Gi-gwan Park
  • Patent number: 10475707
    Abstract: A method of manufacturing a semiconductor device includes forming a first fin-type pattern and a second fin-type pattern which are separated by a first trench between facing ends thereof, forming a first insulating layer filling the first trench, removing a portion of the first insulating layer to form a second trench on the first insulating layer, and forming a third trench by enlarging a width of the second trench.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: November 12, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Gi Gwan Park, Jung Gun You, Ki II Kim, Sug Hyun Sung, Myung Yoon Um
  • Patent number: 10461189
    Abstract: An integrated circuit device includes a fin-type active area protruding from a substrate; a plurality of liners sequentially covering lower side walls of the fin-type active area; a device isolation layer covering the lower side walls of the fin-type active area with the plurality of liners between the device isolation layer and the fin-type active area; and a gate insulating layer extending to cover a channel region of the fin-type active area, the plurality of liners, and the device isolation layer, and including protrusions located on portions of the gate insulating layer which cover the plurality of liners.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: October 29, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sug-Hyun Sung, Jung-gun You, Gi-gwan Park, Ki-il Kim
  • Publication number: 20190189804
    Abstract: A semiconductor device includes first and second fin patterns on a substrate and extending apart from each other, a field insulating film on the substrate and surrounding parts of the first and second fin patterns, a first gate structure on the first fin pattern and intersecting the first fin pattern, a second gate structure on the second fin pattern and intersecting the second fin pattern, and a separating structure protruding from a top surface of the field insulating film and separating the first and second gate structures, the field insulating film and the separating structure including a same insulating material.
    Type: Application
    Filed: July 25, 2018
    Publication date: June 20, 2019
    Inventors: Jung Gun YOU, Dong Hyun KIM, Byoung-Gi KIM, Yun Suk NAM, Yeong Min JEON, Sung Chul PARK, Dae Won HA
  • Publication number: 20190131300
    Abstract: Semiconductor devices are provided including a first fin-shaped pattern having first and second sidewalls facing one another and a field insulating film contacting at least a portion of the first fin-shaped pattern. The first fin-shaped pattern includes a lower portion of the first fin-shaped pattern contacting the field insulating film; an upper portion of the first fin-shaped pattern not contacting the field insulating film; a first boundary between the lower portion of the first fin-shaped pattern and the upper portion of the first fin-shaped pattern; and a first fin center line perpendicular to the first boundary and meeting the top of the upper portion of the first fin-shaped pattern. The first sidewall of the upper portion of the first fin-shaped pattern and the second sidewall of the upper portion of the first fin-shaped pattern are asymmetric with respect to the first fin center line.
    Type: Application
    Filed: December 27, 2018
    Publication date: May 2, 2019
    Inventors: JUNG-GUN YOU, Se-wan Park, Baik-Min Sung, Bo-Cheol Jeong