Abstract: A memory device includes a first memory cell, a second memory cell, a precharge circuit, a sense amplifier, a switch circuit, and a controller. The first memory cell is connected to a first bit line, the second memory cell is connected to a second bit line, and the precharge circuit connected between the first bit line and the second bit line. The sense amplifier includes a first input terminal and a second input terminal. The switch circuit is connected to the first bit line and the first input terminal and to the second bit line and the second input terminal and is configured to control a connection between the first bit line and the first input terminal and a connection between the second bit line and the second input terminal in response to a switch signal. The controller is configured to generate the switch signal in response to a command.

Abstract: A memory device may include a memory cell array, a bloom-filter circuit, a cache memory circuit, and a selecting circuit. The bloom-filter circuit may be configured to output a determination result signal that indicates that there is a possibility that a received address is one of failed addresses corresponding to failed cells of the memory cell array. The cache memory circuit may be configured to, store the failed addresses and a first set of data corresponding to the respective failed addresses, and configured to, when the determination result signal indicates a possibility, provide a comparison result signal by determining whether received address coincides with one of the failed addresses. The selecting circuit may be configured to output either first data of the first set of data or second data of the memory cell array corresponding to the received address based on determination result signal and comparison result signal.

Abstract: This disclosure concerns a method and apparatus of generating a signal from multi-site radars using the same channel. This disclosure provides the method comprising generating a first signal, generating a plurality of time-shifted signals by shifting the first signal by different time shift values, computing correlation values between the first signal and the time-shifted signals, selecting second signals whose correlation values are not more than a threshold from among the time-shifted signals, in a case where two of the second signals are selected, computing a sum of correlation values for all selectable signal combinations, and selecting a signal combination that leads to a minimum sum of correlation values from among the signal combinations.

Abstract: A multi-band built-in antenna of a portable terminal is provided. The antenna includes a first antenna radiator on a front surface of a substrate (e.g., a main board), and a second antenna radiator on an opposite surface of the substrate. The substrate has ground surfaces on both sides separated from a non-ground area on which the radiators are disposed. The first radiator may be in the form of a Planar Inverted F Antenna (PIFA), with a first end branched off into two parts, one part used for power feeding and the other part electrically coupled to the ground surface. The first radiator has a portion that extends from the first end to an opposite end. The second radiator is continuous from the opposite end of the first radiator through a via (hole) in the main board.

Abstract: Atomic memory access requests are handled using a variety of systems and methods. According to one example method, a data-processing circuit having an address-request generator that issues requests to a common memory implements a method of processing the requests using a memory-access intervention circuit coupled between the generator and the common memory. The method identifies a current atomic-memory access request from a plurality of memory access requests. A data set is stored that corresponds to the current atomic-memory access request in a data storage circuit within the intervention circuit. It is determined whether the current atomic-memory access request corresponds to at least one previously-stored atomic-memory access request. In response to determining correspondence, the current request is implemented by retrieving data from the common memory. The data is modified in response to the current request and at least one other access request in the memory-access intervention circuit.

Abstract: Embodiments of the present invention are directed to optoelectronic network switches. In one embodiment, an optoelectronic switch includes a set of roughly parallel input waveguides and a set of roughly parallel output waveguides positioned roughly perpendicular to the input waveguides. Each of the output waveguides crosses the set of input waveguides. The optoelectronic switch includes at least one switch element configured to switch one or more optical signals transmitted on one or more input waveguides onto one or more crossing output waveguides.

Abstract: Various embodiments of the present invention are directed multi-core memory modules. In one embodiment, a memory module (500) includes memory chips, and a demultiplexer register (502) electronically connected to each of the memory chips and a memory controller. The memory controller groups one or more of the memory chips into at least one virtual memory device in accordance with changing performance and/or energy efficiency needs. The demultiplexer register (502) is configured to receive a command indentifying one of the virtual memory devices and send the command to the memory chips of the identified virtual memory device. In certain embodiments, the memory chips can be dynamic random access memory chips.

Abstract: A circuit switched optical interconnection fabric includes a first hollow metal waveguide and a second hollow metal waveguide which intersects the first hollow metal waveguide to form an intersection. An optical element within the intersection is configured to selectively direct an optical signal between the first hollow metal waveguide and a second hollow metal waveguide.

Abstract: A semiconductor memory device may include a plurality of data input/output DQ pads and a plurality of first and second memory cell arrays. Each path of a first set of data paths from each of the plurality of first memory cell arrays to a corresponding DQ pad is physically shorter than each path of a second set of data paths from each of the plurality of second memory cell arrays to the corresponding DQ pad. Each of the plurality of first memory cell arrays is a designated first-speed access cell array and each of the plurality of second memory cell arrays is a designated second-speed access cell array, the second-speed being slower than the first-speed. A size of the each of the plurality of first memory cell arrays is smaller than a size of the each of the plurality of second memory cell arrays.

Abstract: Various embodiments of the present invention are directed to methods that enable a memory controller to choose a particular operation mode for virtual memory devices of a memory module based on dynamic program behavior. In one embodiment, a method for determining an operation mode for each virtual memory device of a memory module includes selecting a metric (1001) that provides a standard by which performance and/or energy efficiency of the memory module is optimized during execution of one or more applications on a multicore processor. For each virtual memory device (1005), the method also includes collecting usage information (1006) associated with the virtual memory device over a period of time, determining an operation mode (1007) for the virtual memory device based on the metric and usage information, and entering the virtual memory device into the operation mode (1103, 1105, 1107, 1108).

Abstract: Various embodiments of the present invention are directed to methods and systems for transmitting optical signals from a source to a plurality of receiving devices. In one method embodiment, an optical enablement signal is transmitted from the source to the plurality of receiving devices. The target receiving device responds to receiving the optical enablement signal by preparing to receive one or more optical data signals. The source transmits the one or more optical data signals to the target receiving device. The remaining receiving devices do not receive the one or more optical data signals.

Abstract: Various embodiments of the present invention are directed a multi-core memory modules. In one embodiment, a memory module (500) includes at least one virtual memory device and a demultiplexer register (502) disposed between the at least one virtual memory device and a memory controller. The demultiplexer register receives a command identifying one of the at least one virtual memory devices from the memory controller and sends the command to the identified virtual memory device. In addition, the at least one virtual memory devices include at least one memory chip.

Abstract: Various embodiments of the present invention are directed to methods and systems for transmitting optical signals from a source to a plurality of receiving devices. In one method embodiment, an optical enablement signal is transmitted from the source to the plurality of receiving devices. The target receiving device responds to receiving the optical enablement signal by preparing to receive one or more optical data signals. The source transmits the one or more optical data signals to the target receiving device. The remaining receiving devices do not receive the one or more optical data signals.

Abstract: Embodiments of the present invention relate to systems and methods for distributing an intentionally skewed optical-clock signal to nodes of a source synchronous computer system. In one system embodiment, a source synchronous system comprises a waveguide, an optical-system clock optically coupled to the waveguide, and a number of nodes optically coupled to the waveguide. The optical-system clock generates and injects a master optical-clock signal into the waveguide. The master optical-clock signal acquiring a skew as it passes between nodes. Each node extracts a portion of the master optical-clock signal and processes optical signals using the portion of the master optical-clock signal having a different skew for the respective extracting node.

Abstract: Illustrated is a computer system and method that includes a Processing Element (PE) to generate a data packet that is routed along a shortest path that includes a plurality of routers in a multiple dimension network. The system and method further include a router, of the plurality of routers, to de-route the data packet from the shortest path to an additional path, the de-route to occur where the shortest path is congested and the additional path links the router and an additional router in a dimension of the multiple dimension network.

Abstract: Various embodiments of the present invention are directed to methods and systems for transmitting optical signals from a source to a plurality of receiving devices. In one method embodiment, an optical enablement signal is transmitted (401) from the source to the plurality of receiving devices. The target receiving device responds to receiving the optical enablement signal by preparing to receive one or more optical data signals. The source transmits the one or more optical data signals to the target receiving device. The remaining receiving devices do not receive the one or more optical data signals.

Abstract: Methods and apparatus to determine and implement multidimensional network topologies are disclosed. An example method disclosed herein comprises receiving an input parameter for determining a multidimensional network topology for a network interconnecting a plurality of devices, and determining a set of multidimensional network topologies, each multidimensional network topology of the set comprising a respective plurality of nodes to interconnect the plurality of devices, each node in each multidimensional network topology of the set being fully connected with all neighbor nodes in each dimension of the multidimensional network topology, and each multidimensional network topology of the set satisfying a first constraint based on the input parameter.

Abstract: A circuit switched optical interconnection fabric includes a first hollow metal waveguide and a second hollow metal waveguide which intersects the first hollow metal waveguide to form an intersection. An optical element within the intersection is configured to selectively direct an optical signal between the first hollow metal waveguide and a second hollow metal waveguide.

Abstract: Various embodiments of the present invention relate to electronically tunable ring resonators. In one embodiment of the present invention, a resonator structure (300,1200) includes an inner resonator disposed on a surface of a substrate, and a phase-change layer (304,1204) covering the resonator. The resonance wavelength of the resonator structure can be selected by applying of a first voltage that changes the effective refractive index of the inner resonator and by applying of a second voltage that changes the effective refractive index of the phase-change layer.

Abstract: Methods and apparatus to determine and implement multidimensional network topologies are disclosed. An example method disclosed herein comprises receiving an input parameter for determining a multidimensional network topology for a network interconnecting a plurality of devices, and determining a set of multidimensional network topologies, each multidimensional network topology of the set comprising a respective plurality of nodes to interconnect the plurality of devices, each node in each multidimensional network topology of the set being fully connected with all neighbor nodes in each dimension of the multidimensional network topology, and each multidimensional network topology of the set satisfying a first constraint based on the input parameter.