Patents by Inventor Jung-Hyun Shin

Jung-Hyun Shin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7442613
    Abstract: A field effect transistor includes a channel region under a gate stack formed on a semiconductor structure. The field effect transistor also includes a drain region formed with a first dopant doping a first side of the channel region, and includes a source region formed with the first dopant doping a second side of the channel region. The drain and source regions are doped asymmetrically such that a first charge carrier profile between the channel and drain regions has a steeper slope than a second charge carrier profile between the channel and source regions.
    Type: Grant
    Filed: October 25, 2006
    Date of Patent: October 28, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-Jae Hur, Kyung-Seok Oh, Joo-Sung Park, Jung-Hyun Shin
  • Patent number: 7439102
    Abstract: A semiconductor fuse box includes a fuse structure and a protective structure disposed between the fuse structure and an integrated circuit structure. The protective structure has at least one irregular side surface. The protective structure (which may also include a pad formed there-under) extends beyond a bottom of the fuse structure. Such an irregular side surface and such an extension of the protective structure minimize propagation of damaging energy to the adjacent integrated circuit structure when a laser beam is directed to the fuse structure.
    Type: Grant
    Filed: November 10, 2006
    Date of Patent: October 21, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min-Sung Kang, Kyung-Seok Oh, Joo-Sung Park, Jung-Hyun Shin
  • Publication number: 20080045120
    Abstract: Disclosed is a stuffed toy including a cover made of fabrics, such as artificial mink, woolen fabric, or stuffed toys sewn in various animals, and a stuffing, such as cotton, cashmilon or foaming substance, filled in the cover, thereby forming a head portion and a body. The stuffed toy includes a heating element, interposed between the cover and the stuffing, which corresponds to an abdomen of the body, for transferring to a user, a power source, installed in a proper position of the cover, for supplying a power to the heating element, and a control unit, installed in a proper position of the cover, for controlling temperature of the heating element and turning the power source on or off. It gives an intimate response to the child when the child carries it in her his arms, so that the child feels a psychical reliance during carrying.
    Type: Application
    Filed: September 28, 2006
    Publication date: February 21, 2008
    Inventors: Sung Joo Moon, Jung Hyun Shin
  • Publication number: 20070057342
    Abstract: A semiconductor fuse box includes a fuse structure and a protective structure disposed between the fuse structure and an integrated circuit structure. The protective structure has at least one irregular side surface. The protective structure (which may also include a pad formed there-under) extends beyond a bottom of the fuse structure. Such an irregular side surface and such an extension of the protective structure minimize propagation of damaging energy to the adjacent integrated circuit structure when a laser beam is directed to the fuse structure.
    Type: Application
    Filed: November 10, 2006
    Publication date: March 15, 2007
    Inventors: Min-Sung Kang, Kyung-Seok Oh, Joo-Sung Park, Jung-Hyun Shin
  • Publication number: 20070034926
    Abstract: A field effect transistor includes a channel region under a gate stack formed on a semiconductor structure. The field effect transistor also includes a drain region formed with a first dopant doping a first side of the channel region, and includes a source region formed with the first dopant doping a second side of the channel region. The drain and source regions are doped asymmetrically such that a first charge carrier profile between the channel and drain regions has a steeper slope than a second charge carrier profile between the channel and source regions.
    Type: Application
    Filed: October 25, 2006
    Publication date: February 15, 2007
    Inventors: Ki-Jae Hur, Kyung-Seok Oh, Joo-Sung Park, Jung-Hyun Shin
  • Patent number: 7154160
    Abstract: A semiconductor fuse box includes a fuse structure and a protective structure disposed between the fuse structure and an integrated circuit structure. The protective structure has at least one irregular side surface. The protective structure (which may also include a pad formed there-under) extends beyond a bottom of the fuse structure. Such an irregular side surface and such an extension of the protective structure minimize propagation of damaging energy to the adjacent integrated circuit structure when a laser beam is directed to the fuse structure.
    Type: Grant
    Filed: October 7, 2004
    Date of Patent: December 26, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min-Sung Kang, Kyung-Seok Oh, Joo-Sung Park, Jung-Hyun Shin
  • Patent number: 7145196
    Abstract: A field effect transistor includes a channel region under a gate stack formed on a semiconductor structure. The field effect transistor also includes a drain region formed with a first dopant doping a first side of the channel region, and includes a source region formed with the first dopant doping a second side of the channel region. The drain and source regions are doped asymmetrically such that a first charge carrier profile between the channel and drain regions has a steeper slope than a second charge carrier profile between the channel and source regions.
    Type: Grant
    Filed: December 2, 2004
    Date of Patent: December 5, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-Jae Hur, Kyung-Seok Oh, Joo-Sung Park, Jung-Hyun Shin
  • Publication number: 20050127407
    Abstract: A field effect transistor includes a channel region under a gate stack formed on a semiconductor structure. The field effect transistor also includes a drain region formed with a first dopant doping a first side of the channel region, and includes a source region formed with the first dopant doping a second side of the channel region. The drain and source regions are doped asymmetrically such that a first charge carrier profile between the channel and drain regions has a steeper slope than a second charge carrier profile between the channel and source regions.
    Type: Application
    Filed: December 2, 2004
    Publication date: June 16, 2005
    Inventors: Ki-Jae Hur, Kyung-Seok Oh, Joo-Sung Park, Jung-Hyun Shin
  • Publication number: 20050106808
    Abstract: A semiconductor device and methods of fabricating the semiconductor device, suitable for preventing electrical bridges between storage nodes without the increase of planar areas. In one embodiment, a semiconductor device comprises a semiconductor substrate and at least one storage node formed over the semiconductor substrate. The storage node has a bottom portion and a sidewall extending upward from a rim of the bottom portion. At least a portion of the sidewall is recessed.
    Type: Application
    Filed: November 16, 2004
    Publication date: May 19, 2005
    Inventors: Suk-Won Yu, Kyung-Seok Oh, Joo-Sung Park, Jung-Hyun Shin
  • Publication number: 20050082635
    Abstract: A semiconductor fuse box includes a fuse structure and a protective structure disposed between the fuse structure and an integrated circuit structure. The protective structure has at least one irregular side surface. The protective structure (which may also include a pad formed there-under) extends beyond a bottom of the fuse structure. Such an irregular side surface and such an extension of the protective structure minimize propagation of damaging energy to the adjacent integrated circuit structure when a laser beam is directed to the fuse structure.
    Type: Application
    Filed: October 7, 2004
    Publication date: April 21, 2005
    Inventors: Min-Sung Kang, Kyung-Seok Oh, Joo-Sung Park, Jung-Hyun Shin
  • Patent number: 5818091
    Abstract: A semiconductor device includes a connection pad layer for securing a contact margin which is formed on a first conductivity-type area whereas electrodes are connected directly through openings on a second conductivity-type area without the connection pad layer. A device fabricated according to this structure yields improved punch-through and junction depth characteristics.
    Type: Grant
    Filed: November 12, 1996
    Date of Patent: October 6, 1998
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-hee Lee, Young-woo Seo, Jung-hyun Shin
  • Patent number: 5591670
    Abstract: A highly integrated semiconductor device and method for manufacturing the same are disclosed. The device has a self-aligned contact structure for increasing a contact margin upon forming a self-aligned buried contact hole. An oxide film of an upper portion of a gate electrode is chamfered in order to form a self-aligned buried contact hole. Therefore, a self-aligned contact hole can be formed without enhancing the step, and as a result, the step between the cell and the peripheral portion of the cell can be reduced.
    Type: Grant
    Filed: June 5, 1995
    Date of Patent: January 7, 1997
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-mo Park, Jung-hyun Shin, Young-hun Park
  • Patent number: 5502336
    Abstract: A highly integrated semiconductor device and method for manufacturing the same are disclosed. The device has a self-aligned contact structure for increasing a contact margin upon forming a self-aligned buried contact hole. An oxide film of an upper portion of a gate electrode is chamfered in order to form a self-aligned buried contact hole. Therefore, a self-aligned contact hole can be formed without enhancing the step, and as a result, the step between the cell and the peripheral portion of the cell can be reduced.
    Type: Grant
    Filed: March 14, 1994
    Date of Patent: March 26, 1996
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-mo Park, Jung-hyun Shin, Young-hun Park
  • Patent number: 5484739
    Abstract: A semiconductor device and manufacturing method thereof is disclosed in which a connection pad layer for securing a contact margin is formed on a first conductivity-type area whereas electrodes are connected directly through openings on a second conductivity-type area without the connection pad layer. In the method, an insulating layer is formed on the overall surface of a substrate. Using a mask pattern for exposing the first conductivity-type area, the insulating layer placed on an exposed portion is anisotropically etched so that the remaining insulating layer serves as an impurity-implantation preventing mask in a succeeding first conductivity-type impurity implantation step. A material layer for the connection pad layer is formed prior to the impurity-implantation step and patterned after the impurity implantation.
    Type: Grant
    Filed: December 8, 1994
    Date of Patent: January 16, 1996
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-hee Lee, Young-woo Seo, Jung-hyun Shin
  • Patent number: 5073510
    Abstract: According to the present invention, the incomplete silicon exposure is prevented by the sufficient overetching after the formation of an etching-stop layer on an oxide layer for protecting a conductive layer from the damage of the protective oxide layer when the self-aligned contact window is formed. Therefore, the thickness of the protective oxide layer can be minimized, and the bend of the chip can be improved whereby the following process will be accomplished easily.
    Type: Grant
    Filed: October 23, 1990
    Date of Patent: December 17, 1991
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Oh-Hyun Kwon, Taek-Yong Jang, Jung-Hyun Shin, Won-Taek Choi
  • Patent number: 5005103
    Abstract: A method of manufacturing folded capacitors comprises the steps of: forming a first storage electrode and a first insulating layer; forming a first plate electrode and a second insulating layer thereon and forming a pad poly thereon; limiting the first plate electrode to a predetermined portion; leaving a spacer; forming a second storage electrode; and depositing a third insulating layer and a second plate electrode thereon. It is possible to manufacture a capacitor with a large capacitance and to simplify the manufacturing processes of the capacitor by using the conventional capacitor manufacturing processes. The folded capacitors with a larger capacitance per unit area can be obtained without making the insulating layer be thinned even if the plane area of the capacitor may be reduced remarkably according to a tendency to high integration density.
    Type: Grant
    Filed: June 5, 1990
    Date of Patent: April 2, 1991
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Oh-Hyun Kwon, Taek-Yong Jang, Jung-Hyun Shin, Won-Taek Choi