Patents by Inventor Jung-Ik Oh

Jung-Ik Oh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10685837
    Abstract: Provided is a staircase-shaped connection structure of a three-dimensional semiconductor device. The device includes an electrode structure on a substrate, the electrode structure including an upper staircase region, a lower staircase region, and a buffer region therebetween. The electrode structure includes horizontal electrodes sequentially stacked on the substrate, the horizontal electrodes include a plurality of pad regions constituting a staircase structure of each of the upper and lower staircase regions, and the buffer region has a width that is larger than that of each of the pad regions.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: June 16, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Ik Oh, Daehyun Jang, Ha-Na Kim, Kyoungsub Shin
  • Publication number: 20190139755
    Abstract: Provided is a staircase-shaped connection structure of a three-dimensional semiconductor device. The device includes an electrode structure on a substrate, the electrode structure including an upper staircase region, a lower staircase region, and a buffer region therebetween. The electrode structure includes horizontal electrodes sequentially stacked on the substrate, the horizontal electrodes include a plurality of pad regions constituting a staircase structure of each of the upper and lower staircase regions, and the buffer region has a width that is larger than that of each of the pad regions.
    Type: Application
    Filed: January 4, 2019
    Publication date: May 9, 2019
    Inventors: Jung-Ik OH, Daehyun JANG, Ha-Na KIM, Kyoungsub SHIN
  • Patent number: 10236442
    Abstract: Provided herein are methods of fabricating a magnetic memory device including forming magnetic tunnel junction patterns on a substrate, forming an interlayered insulating layer on the substrate to cover the magnetic tunnel junction patterns, forming a conductive layer on the interlayered insulating layer, patterning the conductive layer to form interconnection patterns electrically connected to the magnetic tunnel junction patterns, and performing a cleaning process on the interconnection patterns. The cleaning process is performed using a gas mixture of a first gas and a second gas. The first gas contains a hydrogen element (H), and the second gas contains a source gas different from that of the first gas.
    Type: Grant
    Filed: August 3, 2016
    Date of Patent: March 19, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jaehun Seo, Jong-Kyu Kim, Jung-Ik Oh, Inho Kim, Jongchul Park, Gwang-Hyun Baek, Hyun-woo Yang
  • Patent number: 10211053
    Abstract: Provided is a staircase-shaped connection structure of a three-dimensional semiconductor device. The device includes an electrode structure on a substrate, the electrode structure including an upper staircase region, a lower staircase region, and a buffer region therebetween. The electrode structure includes horizontal electrodes sequentially stacked on the substrate, the horizontal electrodes include a plurality of pad regions constituting a staircase structure of each of the upper and lower staircase regions, and the buffer region has a width that is larger than that of each of the pad regions.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: February 19, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Ik Oh, Daehyun Jang, Ha-Na Kim, Kyoungsub Shin
  • Patent number: 10199566
    Abstract: A semiconductor device includes a magnetic tunnel junction structure on a lower electrode, an intermediate electrode on the magnetic tunnel junction structure, and an upper electrode on the intermediate electrode, wherein the intermediate electrode includes a lower portion and an upper portion having a side surface profile different from that of the lower portion.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: February 5, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-Ik Oh, Jong-Kyu Kim, Jongchul Park, Gwang-Hyun Baek, Kyungrae Byun, Hyun-Woo Yang
  • Publication number: 20180197732
    Abstract: Provided is a staircase-shaped connection structure of a three-dimensional semiconductor device. The device includes an electrode structure on a substrate, the electrode structure including an upper staircase region, a lower staircase region, and a buffer region therebetween. The electrode structure includes horizontal electrodes sequentially stacked on the substrate, the horizontal electrodes include a plurality of pad regions constituting a staircase structure of each of the upper and lower staircase regions, and the buffer region has a width that is larger than that of each of the pad regions.
    Type: Application
    Filed: March 2, 2018
    Publication date: July 12, 2018
    Inventors: JUNG-IK OH, DAEHYUN JANG, HA-NA KIM, KYOUNGSUB SHIN
  • Publication number: 20180175109
    Abstract: A variable resistance memory device including a first electrode line; a cell structure including a variable resistance layer on the first electrode line and a first blocking layer protecting the variable resistance layer; and a second electrode line on the cell structure, wherein the first blocking layer is on at least one of an upper surface, a lower surface, and the upper and lower surfaces of the variable resistance layer, and the first blocking layer includes a metal layer or a carbon-containing conductive layer.
    Type: Application
    Filed: October 30, 2017
    Publication date: June 21, 2018
    Inventors: Hye-jin CHOI, Jung-ik OH, Bok-yeon WON, Gwang-hyun BAEK
  • Patent number: 9941122
    Abstract: Provided is a staircase-shaped connection structure of a three-dimensional semiconductor device. The device includes an electrode structure on a substrate, the electrode structure including an upper staircase region, a lower staircase region, and a buffer region therebetween. The electrode structure includes horizontal electrodes sequentially stacked on the substrate, the horizontal electrodes include a plurality of pad regions constituting a staircase structure of each of the upper and lower staircase regions, and the buffer region has a width that is larger than that of each of the pad regions.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: April 10, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Ik Oh, Daehyun Jang, Ha-Na Kim, Kyoungsub Shin
  • Patent number: 9876165
    Abstract: A method for forming a pattern, the method including forming an etch target layer on a substrate; patterning the etch target layer to form patterns; and performing a pre-oxidation trim process a plurality of times, the pre-oxidation trim process including performing an oxidation process to form an insulating layer on a sidewall of each of the patterns; and performing a sputter etch process to remove at least a portion of the insulating layer.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: January 23, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Kuk Kim, Jong-Kyu Kim, Jongchul Park, Inho Kim, Gwang-Hyun Baek, Jung-Ik Oh
  • Publication number: 20180006219
    Abstract: In method of manufacturing a semiconductor memory device, a selection layer and a variable resistance layer may be sequentially formed on a substrate. A preliminary first mask extending in a first direction may be formed on the variable resistance layer. An upper mask extending in a second direction crossing the first direction may be formed on the variable resistance layer and the preliminary first mask. The preliminary first mask may be etched using the upper mask as an etching mask to form a first mask having a pillar shape. The variable resistance layer and the selection layer may be anisotropically etched using the first mask as an etching mask to form a pattern structure including a variable resistance pattern and selection pattern sequentially stacked. The pattern structure may have a pillar shape. Damages to the pattern structure may decrease.
    Type: Application
    Filed: January 25, 2017
    Publication date: January 4, 2018
    Inventors: Jae-Hun SEO, Jung-Ik OH, Yoo-Chul KONG, Woo-Ram KIM, Jong-Chul PARK, Gwang-Hyun BAEK, Bok-Yeon WON, Hye-Jin CHOI
  • Publication number: 20170110656
    Abstract: Provided herein are methods of fabricating a magnetic memory device including forming magnetic tunnel junction patterns on a substrate, forming an interlayered insulating layer on the substrate to cover the magnetic tunnel junction patterns, forming a conductive layer on the interlayered insulating layer, patterning the conductive layer to form interconnection patterns electrically connected to the magnetic tunnel junction patterns, and performing a cleaning process on the interconnection patterns. The cleaning process is performed using a gas mixture of a first gas and a second gas. The first gas contains a hydrogen element (H), and the second gas contains a source gas different from that of the first gas.
    Type: Application
    Filed: August 3, 2016
    Publication date: April 20, 2017
    Inventors: Jaehun Seo, Jong-Kyu Kim, Jung-Ik Oh, Inho Kim, Jongchul Park, Gwang-Hyun Baek, Hyun-woo Yang
  • Publication number: 20170098759
    Abstract: A semiconductor device includes a magnetic tunnel junction structure on a lower electrode, an intermediate electrode on the magnetic tunnel junction structure, and an upper electrode on the intermediate electrode, wherein the intermediate electrode includes a lower portion and an upper portion having a side surface profile different from that of the lower portion.
    Type: Application
    Filed: July 27, 2016
    Publication date: April 6, 2017
    Inventors: Jung-Ik OH, Jong-Kyu KIM, Jongchul PARK, Gwang-Hyun BAEK, Kyungrae BYUN, Hyun-Woo YANG
  • Patent number: 9608040
    Abstract: A memory device including a substrate, an insulating layer on the substrate, the insulating layer including a first region having a first top surface and a second region having a second top surface, the second top surface being lower than the first top surface with respect to the substrate, the first region including a first through hole penetrating therethrough, the second region including a second through hole penetrating therethrough, a first conductive pattern filling the first through hole, a second conductive pattern at least partially filling the second through hole, a magnetic tunnel junction pattern on the first conductive pattern, and a contact plug coupled to the second conductive pattern may be provided. Further, a method of fabricating the memory device also may be provided.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: March 28, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Gwang-Hyun Baek, Inho Kim, Jong-Kyu Kim, Jongchul Park, Jung-Ik Oh
  • Publication number: 20170069526
    Abstract: A chuck assembly includes a chuck to hold a substrate, and a pillar coupled to the chuck to support the chuck, an axis of the pillar passing through a center of the pillar in a longitudinal direction of the pillar, wherein the chuck has a top surface, which is inclined with respect to the axis of the pillar, the top surface of the chuck being precessionally rotatable about the axis of the pillar.
    Type: Application
    Filed: June 1, 2016
    Publication date: March 9, 2017
    Inventors: Jongsoon PARK, Jong-Kyu KIM, Jung-Ik OH, Sang-Kuk KIM, Jongchul PARK
  • Publication number: 20170062709
    Abstract: A method for forming a pattern, the method including forming an etch target layer on a substrate; patterning the etch target layer to form patterns; and performing a pre-oxidation trim process a plurality of times, the pre-oxidation trim process including performing an oxidation process to form an insulating layer on a sidewall of each of the patterns; and performing a sputter etch process to remove at least a portion of the insulating layer.
    Type: Application
    Filed: June 13, 2016
    Publication date: March 2, 2017
    Inventors: Sang-Kuk KIM, Jong-Kyu KIM, Jongchul PARK, Inho KIM, Gwang-Hyun BAEK, Jung-Ik OH
  • Patent number: 9543307
    Abstract: A method of manufacturing a vertical memory device includes: providing a substrate including a cell array region and a peripheral circuit region; forming a mold structure in the cell array region; forming a mold protection film in a portion of the cell array region and the peripheral circuit region, the mold protection film contacting the mold structure; forming an opening for a common source line that passes through the mold structure and extends in a first direction perpendicular to a top surface of the substrate; forming a peripheral circuit contact hole that passes through the mold protection film and extends in the first direction in the peripheral circuit region; and simultaneously forming a first contact plug and a second contact plug, respectively, in the opening for the common source line and in the peripheral circuit contact hole.
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: January 10, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ha-Na Kim, Dae-Hyun Jang, Jung-Ik Oh
  • Publication number: 20160372347
    Abstract: Provided are a substrate processing apparatus capable of performing a semiconductor process using a plasma and a method of forming a semiconductor device using the same. The substrate processing apparatus includes a process chamber, a high vacuum pump, an exhaust flow path between the high vacuum pump and the process chamber, and a vacuum valve in the exhaust flow path. The vacuum valve includes a first valve and a second valve having a smaller orifice than the first valve.
    Type: Application
    Filed: January 28, 2016
    Publication date: December 22, 2016
    Inventors: Hyuk KIM, Ha-Na KIM, Kyoungsub SHIN, Jung-Ik OH
  • Publication number: 20160372322
    Abstract: Provided is a staircase-shaped connection structure of a three-dimensional semiconductor device. The device includes an electrode structure on a substrate, the electrode structure including an upper staircase region, a lower staircase region, and a buffer region therebetween. The electrode structure includes horizontal electrodes sequentially stacked on the substrate, the horizontal electrodes include a plurality of pad regions constituting a staircase structure of each of the upper and lower staircase regions, and the buffer region has a width that is larger than that of each of the pad regions.
    Type: Application
    Filed: August 29, 2016
    Publication date: December 22, 2016
    Inventors: JUNG-IK OH, DAEHYUN JANG, HA-NA KIM, KYOUNGSUB SHIN
  • Patent number: 9455268
    Abstract: Provided is a staircase-shaped connection structure of a three-dimensional semiconductor device. The device includes an electrode structure on a substrate, the electrode structure including an upper staircase region, a lower staircase region, and a buffer region therebetween. The electrode structure includes horizontal electrodes sequentially stacked on the substrate, the horizontal electrodes include a plurality of pad regions constituting a staircase structure of each of the upper and lower staircase regions, and the buffer region has a width that is larger than that of each of the pad regions.
    Type: Grant
    Filed: October 22, 2014
    Date of Patent: September 27, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Ik Oh, Daehyun Jang, Ha-Na Kim, Kyoungsub Shin
  • Patent number: 9419008
    Abstract: According to example embodiments, a method of fabricating a semiconductor device includes: forming a preliminary stack structure including upper and lower preliminary stack structures by alternately stacking a plurality of interlayer insulating and sacrificial layers on a cell, first pad area, dummy area and second pad area of a substrate; removing an entire portion of the upper preliminary stack structure on the second pad area; forming a first mask defining openings over parts of the first and second pad areas; etching an etch depth corresponding to ones of the plurality of interlayer insulating and sacrificial layers through a remaining part of the preliminary stack structure exposed by the first mask; and repetitively performing a first staircase forming process that includes shrinking sides of the first mask and etching the etch depth through remaining parts of the plurality of interlayer insulating and sacrificial layers exposed by the shrunken first mask.
    Type: Grant
    Filed: July 9, 2015
    Date of Patent: August 16, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Ik Oh, Dae-Hyun Jang, Kyoung-Sub Shin