Abstract: A linear motor design variable verification method and a linear motor design variable optimization method are disclosed. The linear motor design variable verification method includes a first step of deriving a magnetic permeability matrix of a linear motor from a linear motor design variable; a second step of deriving a Maxwell matrix of the linear motor from the magnetic permeability matrix of the linear motor via LU decomposition; a third step of deriving, from the Maxwell matrix of the linear motor, at least one verification target physical quantity selected from a group including a force of the linear motor, a magnetic flux linkage passing through each of coils of a stator of the linear motor, a counter electromotive force of the linear motor, and an inductance of the linear motor; and a fourth step of comparing the derived verification target physical quantity with a predetermined reference value, and determining whether a target verification condition is satisfied, based on the comparing result.

Abstract: Semiconductor devices are provided. The semiconductor devices includes a landing pad on a substrate, a lower electrode on the landing pad and connected to the landing pad, a capacitor dielectric film that is on the lower electrode and includes both a tetragonal crystal system and an orthorhombic crystal system, a first doping layer that is between the lower electrode and the capacitor dielectric film and includes a first metal, and an upper electrode on the capacitor dielectric film.

Abstract: Provided is an ultrasonic welding system and a power module package for a power converting apparatus to which a substrate where connection members are ultrasonic welded by using the system is applied, wherein the ultrasonic welding system includes a waffle pack 110 on which connection members 10 to be ultrasonic welded onto a substrate 20 are arranged in a specific form, a centering aligning unit 120 which aligns and centers the connection members 10 transferred from the waffle pack 110, an ultrasonic welding part 130 which fixes the substrate 20 and ultrasonic welds the connection members 10 aligned by the centering aligning unit 120 onto the substrate 20, and a picker 140 which separately picks the connection members 10 from the waffle pack 110 to be transferred to the centering aligning unit 120 and re-picks the aligned connection members 10 from the centering aligning unit 120 to be transferred to ultrasonic welding positions on the substrate 20 fixed to the ultrasonic welding part 130, wherein the connec

Abstract: A multilayer electronic component includes a plurality of capacitance forming portions including a first dielectric layer and an internal electrode disposed in a first direction, and an intermediate layer disposed between capacitance forming portions adjacent to each other and including a second dielectric layer, a body including first and second surfaces opposing each other in the first direction, third and fourth surfaces connected to the first and second surfaces and opposing each other in a second direction, and fifth and sixth surfaces connected to the first to fourth surfaces and opposing each other in a third direction; and an external electrode disposed on the body and connected to the internal electrode. The second dielectric layer includes graphene. The first dielectric layer does not include graphene, or includes graphene in a content less than a content of graphene included in the second dielectric layer.

Abstract: A capacitor structure is provided. The capacitor structure comprises an upper electrode, a lower electrode including a lower electrode film and a lower interface electrode film, a capacitor dielectric film between the lower electrode and the upper electrode, and an interface blocking film between the lower electrode and the capacitor dielectric film, the interface blocking film being in contact with the capacitor dielectric film and the lower interface electrode film, wherein the interface blocking film includes a first metal oxide containing a first metal element, the lower interface electrode film includes a second conductive metal oxide containing a second metal element different from the first metal element, the capacitor dielectric film does not include the first metal oxide, and a thickness of the lower interface electrode film is greater than that of the interface blocking film.

Abstract: An electronic device may include a circuit board, radiators disposed on the circuit board, and provided with a first feeding signal to transmit or receive a wireless signal in a first frequency band; and a ground disposed on the circuit board to provide a reference potential for the radiators. The radiators and a whole or a portion of the ground may be provided with an additional feeding signal to transmit or receive a wireless signal in various frequency bands that are lower than the first frequency band.

Abstract: A semiconductor memory device comprises, a substrate, a mold structure including gate electrodes and mold insulating films alternately stacked on the substrate, and a channel structure penetrating the mold structure, wherein the channel structure comprises a semiconductor pattern and a dielectric film on the semiconductor pattern, wherein the dielectric film comprises a first crystalline film in contact with the gate electrodes and a second crystalline film between the first crystalline film and the semiconductor pattern, wherein the first crystalline film includes a first matrix and a first impurity and the second crystalline film includes a second matrix and a second impurity, wherein each of the first matrix and the second matrix comprises at least one of HfO2, HfxZr1-xO2 (0.5<x<1) and Hf1-yZryO2 (0.5<y<1), and wherein each of the first impurity and the second impurity is 10 at % or less of the first crystalline film and second crystalline film, respectively.

Abstract: A coil component includes: a body having a first and a second surface opposing each other, and a third and a fourth surface opposing each other and connecting the first surface and second surface; a support member disposed within the body; first and second coils disposed on the support member; first and third external electrodes disposed on the body and connected to the first coil; second and fourth external electrodes disposed on the body and connected to the second coil; a first via electrode disposed within the body and connecting the first coil and the first external electrode; and a second via electrode disposed within the body and connecting the second coil and the second external electrode, wherein the first to fourth external electrodes are disposed on the first surface, the third external electrode extends onto the third surface, and the fourth external electrode extends onto the fourth surface.

Abstract: A display device includes, a display panel including a first area and a bending area adjacent to the first area in a first direction, a window on the display panel and including a light blocking member, a cover panel on the display panel, and a cover spacer on the display panel. The cover panel includes, first and second cushion layers, a heat dissipation layer between the first and second cushion layers, a light blocking layer between the first and second cushion layers and overlapping the heat dissipation layer, a base film between the display panel and the first cushion layer, and an upper bonding layer between the base film and the display panel. The light blocking layer and the heat dissipation layer overlap the light blocking member, and have ends protruding further in the first direction than ends of the upper bonding layer, the base film, and the cover spacer.

Abstract: A coil component includes a body, a coil disposed in the body, an external electrode disposed on one surface of the body and including at least one recess, and a via electrode disposed in the body and connecting the coil to the external electrode.

Abstract: Provided is an apparatus for attaching semiconductor parts. The apparatus includes a substrate loading unit, at least one semiconductor part loader, a first vision examination unit, at least one semiconductor part picker, at least one adhesive hardening unit, and a substrate unloading unit, wherein the substrate loading unit supplies a substrate on which semiconductor units are arranged, the at least one semiconductor part loader supplies semiconductor parts, the first vision examination unit examines arrangement states of the semiconductor units, the at least one semiconductor part picker mounts semiconductor parts in the semiconductor units, the at least one adhesive hardening unit hardens and attaches adhesives interposed between the semiconductor units and the semiconductor parts, and the substrate unloading unit releases the substrate on which semiconductor parts are mounted.

Abstract: A multilayer ceramic electronic component includes a body including a dielectric layer, first and second internal electrodes, a stacked portion including first and second surfaces opposing each other in a stacking direction of the first and second internal electrodes, third and fourth surfaces connected to the first and second surfaces and opposing each other, and fifth and sixth surfaces connected to the first and second surfaces, connected to the third and fourth surfaces, and opposing each other, and a coating layer disposed on the first to sixth surfaces of the stacked portion and having first and second connection portions; and first and second external electrodes connected to the first and second internal electrodes, respectively, and arranged on the third and fourth surfaces of the body, wherein the first and second internal electrodes are respectively connected to the first and second external electrodes through the first and second connection portions.

Abstract: A device for manufacturing a semiconductor device is provided. The device for manufacturing a semiconductor device includes a tube extending in a first direction, and defining a reaction space therein and configured to accommodate a boat that is configured to receive a plurality of substrates therein, and first and second nozzles each extending in the first direction inside the tube, and being apart from each other on a plane that is perpendicular to the first direction and parallel to upper surfaces of the substrates, wherein the first and second nozzles include a plurality of first injection ports and a plurality of first second injection ports that are configured inject different gases toward a center of the reaction space, respectively, and a plurality of second injection ports are placed in a region between a corresponding pair of adjacent ones of the plurality of first injection ports along the first direction.

Abstract: Provided is a method for controlling an interaction undo/redo interface. The method for controlling an interaction undo/redo interface includes causing interaction to be performed between a plurality of virtual objects created in a three-dimensional virtual space and a user, wherein the interaction is performed by recognition of the user's gesture, and activating the interaction undo interface or the interaction redo interface in response to a gesture not corresponding to the user's interaction gesture.

Abstract: A multilayer electronic component includes a plurality of capacitance forming portions including a first dielectric layer and an internal electrode disposed in a first direction, and an intermediate layer disposed between capacitance forming portions adjacent to each other and including a second dielectric layer, a body including first and second surfaces opposing each other in the first direction, third and fourth surfaces connected to the first and second surfaces and opposing each other in a second direction, and fifth and sixth surfaces connected to the first to fourth surfaces and opposing each other in a third direction; and an external electrode disposed on the body and connected to the internal electrode. The second dielectric layer includes graphene. The first dielectric layer does not include graphene, or includes graphene in a content less than a content of graphene included in the second dielectric layer.

Abstract: A multilayer ceramic electronic component includes a ceramic body including a dielectric layer and first and second internal electrodes with the dielectric layer interposed therebetween, the dielectric layer and the first and second internal electrodes arranged to be stacked, and a first cover portion disposed on the capacitance portion, and a second cover portion disposed on the capacitance portion, a first external electrode connected to the first internal electrode, and a second external electrode connected to the second internal electrode. The first cover portion and the second cover portion include a cover reinforcing layer including graphene.

Abstract: Semiconductor devices are provided. The semiconductor devices includes a landing pad on a substrate, a lower electrode on the landing pad and connected to the landing pad, a capacitor dielectric film that is on the lower electrode and includes both a tetragonal crystal system and an orthorhombic crystal system, a first doping layer that is between the lower electrode and the capacitor dielectric film and includes a first metal, and an upper electrode on the capacitor dielectric film.

Abstract: Various embodiments of the present disclosure relate to an apparatus and a method for data transmission using carrier aggregation (CA) in an electronic device. An operating method of an electronic device according to various embodiments of the present disclosure includes: determining a frequency band based on information regarding at least one of a rank or a service, which is applied to frequency bands used for CA; performing impedance matching with reference to the frequency band; and transmitting data by using antennas for which the impedance matching has been performed. Other embodiments are possible.

Abstract: A multilayer capacitor includes a body, a plurality of internal electrodes, and external electrodes. The corners of the cover portions of the body include curved surfaces, a length of each of internal electrodes disposed in the cover portions among the plurality of internal electrodes is smaller than a length of an internal electrode disposed in a central portion, and when a distance from a surface of the body to a closest internal electrode among the plurality of internal electrodes is defined as a margin, a portion of the margin region, located directly above or below the internal electrodes disposed in the cover portions in the stacking direction, includes at least two layers including different densities of dielectric layers.

Abstract: A multilayer ceramic electronic component includes a body including a dielectric layer, first and second internal electrodes, a stacked portion including first and second surfaces opposing each other in a stacking direction of the first and second internal electrodes, third and fourth surfaces connected to the first and second surfaces and opposing each other, and fifth and sixth surfaces connected to the first and second surfaces, connected to the third and fourth surfaces, and opposing each other, and a coating layer disposed on the first to sixth surfaces of the stacked portion and having first and second connection portions; and first and second external electrodes connected to the first and second internal electrodes, respectively, and arranged on the third and fourth surfaces of the body, wherein the first and second internal electrodes are respectively connected to the first and second external electrodes through the first and second connection portions.