Patents by Inventor Jung-Nam Kim
Jung-Nam Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11967669Abstract: A display device is provided including a substrate. A second semiconductor layer is disposed on the substrate. The second semiconductor layer includes Si. A second gate lower electrode overlaps a channel region of the second semiconductor layer. A second gate insulating layer is disposed on the second gate lower electrode. A second gate upper electrode and a light blocking layer are disposed on the second gate insulating layer. A first auxiliary layer is disposed on the second gate upper electrode and the light blocking layer. A first semiconductor layer overlaps the light blocking layer. The first semiconductor layer includes an oxide semiconductor. A first gate electrode overlaps a channel region of the first semiconductor layer. The first auxiliary layer includes an insulating layer including at least one compound selected from SiNx, SiOx, and SiON, and at least one material selected from F, Cl, and C.Type: GrantFiled: June 17, 2022Date of Patent: April 23, 2024Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Jae-Bum Han, Young Gil Park, Jung Hwa Park, Na Ri Ahn, Soo Im Jeong, Ki Nam Kim, Moon Sung Kim
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Adhesive protective film, optical member comprising the same and optical display comprising the same
Patent number: 11958993Abstract: Disclosed herein are an adhesive protective film, an optical member including the same, and an optical display including the same. An adhesive protective film is formed of a composition including a (meth)acrylic binder derived from a monomer mixture including: an alkyl group-containing (meth)acrylic monomer; and at least one selected from among a hydroxyl group-containing (meth)acrylic monomer, a carboxyl group-containing (meth)acrylic monomer, and a polysiloxane (meth)acrylate, the adhesive protective film having an initial peel strength of about 100 gf/inch or less and a peel strength decrease rate of about 50% or less, as calculated according to Equation 1.Type: GrantFiled: May 27, 2021Date of Patent: April 16, 2024Assignee: Samsung SDI Co., Ltd.Inventors: Irina Nam, Tae Ji Kim, Won Kim, Il Jin Kim, Jung Hyo Lee, Oh Hyeon Hwang -
Patent number: 11928171Abstract: An example uniform resource locator (URL) information providing method includes obtaining a text from a document including location information and identifying the location information, transmitting an original URL corresponding to the identified location information to an external apparatus and receiving a shortened URL corresponding to the original URL, generating an optical recognition code corresponding to the received shortened URL and obtaining information related to a content provided from the original URL from the external apparatus based on the original URL, changing the document based on the shortened URL, the optical recognition code, and the information related to the content provided from the original URL, and generating the changed document as page description language data.Type: GrantFiled: September 20, 2021Date of Patent: March 12, 2024Assignee: Hewlett-Packard Development Company, L.P.Inventors: Ji Hyun Yoon, Jung Nam Bae, Yoon Soo Lee, Chul Gee Lee, Tae Soon Kim
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Patent number: 11921301Abstract: The present embodiment relates to a dual lens drive device that comprises: a housing; a first bobbin which is disposed to move in a first direction inside the housing; a second bobbin which is disposed to move in the first direction inside housing and is spaced apart from the first bobbin; a first coil which is disposed on the first bobbin; a second coil which is disposed on the second bobbin; a magnet which is disposed in the housing and faces the first coil and the second coil; a base which is disposed below the housing; a substrate which comprises a circuit member having a third coil disposed to face the magnet between the housing and the base; and a support member which movably supports the housing with respect to the substrate, wherein the housing is integrally formed.Type: GrantFiled: October 18, 2022Date of Patent: March 5, 2024Assignee: LG INNOTEK CO., LTD.Inventors: Kap Jin Lee, Yong Nam Choi, Do Yoon Kim, Min Soo Kim, Jung Hwan Kim, Tae Young Kim
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Publication number: 20210358856Abstract: A method for fabricating a semiconductor device includes forming a low-k dielectric layer, forming a pattern by etching the low-k dielectric layer, and implanting a carbon-containing material into a surface of the pattern.Type: ApplicationFiled: August 20, 2020Publication date: November 18, 2021Inventors: Jung Nam KIM, Jin Gyu PARK, Il Sup JIN, Min Ho HA
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Patent number: 10865563Abstract: A self-assembly hot water mat capable of extending through an assembly, the self-assembly hot water mat capable of being assembled with other self-assembly hot water mats, having four sides, and including a path for circulating hot water includes a plurality of hot water passages formed in the self-assembly hot water mat to provide a plurality of hot water flow paths, an inlet formed at each of the four sides, through which hot water flows in, and an outlet formed at each of the four sides and paired with the inlet, through which hot water flows out.Type: GrantFiled: July 18, 2018Date of Patent: December 15, 2020Inventor: Jung Nam Kim
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Publication number: 20190249432Abstract: Provided is a self-assembly hot water mat capable of extending through assembly. A self-assembly hot water mat capable of being assembled with other self-assembly hot water mats, having four sides, and including a path for circulating hot water includes a plurality of hot water passages formed in the self-assembly hot water mat to provide a plurality of hot water flow paths, an inlet formed at each of the four sides, through which hot water flows in, and an outlet formed at each of the four sides and paired with the inlet, through which hot water flows out.Type: ApplicationFiled: July 18, 2018Publication date: August 15, 2019Inventor: Jung Nam KIM
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Patent number: 10084131Abstract: A method for fabricating an electronic device including a semiconductor memory may include: forming a first interlayer dielectric layer over a substrate to have an opening exposing the substrate; forming a bottom electrode in a portion of the opening to have an exposed top surface; forming a variable resistance material layer along sidewalls of the remaining portion of the opening and the exposed top surface of the bottom electrode; forming a top electrode over the variable resistance material layer so as to fill the opening; etching the first interlayer dielectric layer to a predetermined depth to expose a part of the variable resistance material layer surrounding sidewalls of the top electrode; and removing the part of the variable resistance material layer to form a unit cell.Type: GrantFiled: December 5, 2016Date of Patent: September 25, 2018Assignee: SK hynix Inc.Inventors: Sang-Soo Kim, Jung-Nam Kim
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Patent number: 9679944Abstract: An electronic device is provided. An electronic device according to an example of the disclosed technology includes a semiconductor memory, the semiconductor memory including: a substrate including a recess formed in the substrate; a gate including at least a portion that is buried in the substrate; a junction formed at both sides of the gate in the substrate; and a memory element electrically connected to the junction at one side of the gate, wherein the junction includes: a barrier layer formed over the recess such that a thickness of the barrier layer formed over a bottom surface of the recess is different from that of the barrier layer formed over a side surface of the recess; a contact pad formed over the barrier layer so as to fill the recess; and an impurity region formed in the substrate and located under the contact pad.Type: GrantFiled: April 10, 2015Date of Patent: June 13, 2017Assignee: SK hynix Inc.Inventor: Jung-Nam Kim
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Publication number: 20170084836Abstract: A method for fabricating an electronic device including a semiconductor memory may include: forming a first interlayer dielectric layer over a substrate to have an opening exposing the substrate; forming a bottom electrode in a portion of the opening to have an exposed top surface; forming a variable resistance material layer along sidewalls of the remaining portion of the opening and the exposed top surface of the bottom electrode; forming a top electrode over the variable resistance material layer so as to fill the opening; etching the first interlayer dielectric layer to a predetermined depth to expose a part of the variable resistance material layer surrounding sidewalls of the top electrode; and removing the part of the variable resistance material layer to form a unit cell.Type: ApplicationFiled: December 5, 2016Publication date: March 23, 2017Inventors: Sang-Soo Kim, Jung-Nam Kim
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Patent number: 9515260Abstract: A method for fabricating an electronic device including a semiconductor memory may include: forming a first interlayer dielectric layer over a substrate to have an opening exposing the substrate; forming a bottom electrode in a portion of the opening to have an exposed top surface; forming a variable resistance material layer along sidewalls of the remaining portion of the opening and the exposed top surface of the bottom electrode; forming a top electrode over the variable resistance material layer so as to fill the opening; etching the first interlayer dielectric layer to a predetermined depth to expose a part of the variable resistance material layer surrounding sidewalls of the top electrode; and removing the part of the variable resistance material layer to form a unit cell.Type: GrantFiled: September 21, 2015Date of Patent: December 6, 2016Assignee: SK hynix Inc.Inventors: Sang-Soo Kim, Jung-Nam Kim
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Publication number: 20160308127Abstract: A method for fabricating an electronic device including a semiconductor memory may include: forming a first interlayer dielectric layer over a substrate to have an opening exposing the substrate; forming a bottom electrode in a portion of the opening to have an exposed top surface; forming a variable resistance material layer along sidewalls of the remaining portion of the opening and the exposed top surface of the bottom electrode; forming a top electrode over the variable resistance material layer so as to fill the opening; etching the first interlayer dielectric layer to a predetermined depth to expose a part of the variable resistance material layer surrounding sidewalls of the top electrode; and removing the part of the variable resistance material layer to form a unit cell.Type: ApplicationFiled: September 21, 2015Publication date: October 20, 2016Inventors: Sang-Soo Kim, Jung-Nam Kim
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Publication number: 20160293486Abstract: Devices and methods based on disclosed technology include, among others, an electronic device including silicide layers capable of effectively reducing contact resistance in the electronic device including buried gates and a method for fabricating the electronic device. Specifically, an electronic device in one implementation includes a plurality of buried gates formed in a substrate and silicide layers formed over the substrate between the buried gates and protruding upwardly from the buried gates.Type: ApplicationFiled: June 13, 2016Publication date: October 6, 2016Inventor: Jung-Nam Kim
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Patent number: 9368356Abstract: Devices and methods based on disclosed technology include, among others, an electronic device including silicide layers capable of effectively reducing contact resistance in the electronic device including buried gates and a method for fabricating the electronic device. Specifically, an electronic device in one implementation includes a plurality of buried gates formed in a substrate and silicide layers formed over the substrate between the buried gates and protruding upwardly from the buried gates.Type: GrantFiled: January 2, 2014Date of Patent: June 14, 2016Assignee: SK hynix Inc.Inventor: Jung-Nam Kim
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Publication number: 20160148979Abstract: An electronic device is provided. An electronic device according to an example of the disclosed technology includes a semiconductor memory, the semiconductor memory including: a substrate including a recess formed in the substrate; a gate including at least a portion that is buried in the substrate; a junction formed at both sides of the gate in the substrate; and a memory element electrically connected to the junction at one side of the gate, wherein the junction includes: a barrier layer formed over the recess such that a thickness of the barrier layer formed over a bottom surface of the recess is different from that of the barrier layer formed over a side surface of the recess; a contact pad formed over the barrier layer so as to fill the recess; and an impurity region formed in the substrate and located under the contact pad.Type: ApplicationFiled: April 10, 2015Publication date: May 26, 2016Inventor: Jung-Nam Kim
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Publication number: 20150179259Abstract: An electronic device including a semiconductor memory is provided, wherein the semiconductor memory comprises: a substrate in which first to third regions are provided; first to third trenches formed in the first to third regions, respectively, and having a different line width from each other; and first to third device isolation layers formed in the first to third trenches, respectively, wherein the first device isolation layer includes a stack structure of a first insulation layer and a second insulation layer, the second device isolation layer includes the first insulation layer formed over a part of a bottom and one sidewall of the second trench, the second insulation layer having a stepped type and a third insulation layer which is formed over the second insulation layer, and the third device isolation layer includes a stack structure of the first to third insulation layers.Type: ApplicationFiled: November 11, 2014Publication date: June 25, 2015Inventors: Jung-Nam Kim, Jong-Han Shin, Sung-Jun Kim, Sang-Soo Kim
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Publication number: 20150056772Abstract: The present invention provides a semiconductor device including a buried gate and a method for fabricating the same, in which the width of a contact plug may not exceed a predetermined width. The method including forming a plurality of trenches over a substrate using the mask pattern, forming a gate insulating film in each of the plurality of trenches, forming a plurality of gate electrodes filling portions of the plurality of trenches, removing an exposed gate insulating film formed over each of the plurality of gate electrodes in each of the plurality of the trenches, forming a plurality of sealing films filling remaining portions of the plurality of trenches, and forming a plurality of contact plugs over the substrate between the trenches.Type: ApplicationFiled: November 4, 2014Publication date: February 26, 2015Inventors: Jung-Nam KIM, Sang-Soo KIM
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Publication number: 20140256103Abstract: Devices and methods based on disclosed technology include, among others, an electronic device including silicide layers capable of effectively reducing contact resistance in the electronic device including buried gates and a method for fabricating the electronic device. Specifically, an electronic device in one implementation includes a plurality of buried gates formed in a substrate and silicide layers formed over the substrate between the buried gates and protruding upwardly from the buried gates.Type: ApplicationFiled: January 2, 2014Publication date: September 11, 2014Applicant: SK HYNIX INC.Inventor: Jung-Nam Kim
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Patent number: 8692223Abstract: A resistance variable memory device includes: a first electrode; a second electrode; a resistance variable layer interposed between the first electrode and the second electrode; and nano particles that are disposed in the resistance variable layer and have a lower dielectric constant than the resistance variable layer.Type: GrantFiled: August 28, 2012Date of Patent: April 8, 2014Assignee: SK Hynix Inc.Inventors: Ji-Won Moon, Moon-Sig Joo, Sung-Hoon Lee, Jung-Nam Kim
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Publication number: 20140061779Abstract: The present invention provides a semiconductor device including a buried gate and a method for fabricating the same, in which the width of a contact plug may not exceed a predetermined width. The method including forming a plurality of trenches over a substrate using the mask pattern, forming a gate insulating film in each of the plurality of trenches, forming a plurality of gate electrodes filling portions of the plurality of trenches, removing an exposed gate insulating film formed over each of the plurality of gate electrodes in each of the plurality of the trenches, forming a plurality of sealing films filling remaining portions of the plurality of trenches, and forming a plurality of contact plugs over the substrate between the trenches.Type: ApplicationFiled: December 11, 2012Publication date: March 6, 2014Applicant: SK HYNIX INC.Inventors: Jung-Nam KIM, Sang-Soo KIM