Patents by Inventor Jung S. Goo

Jung S. Goo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5477072
    Abstract: An EEPROM cell and a method for fabricating the same are disclosed.The EEPROM cell fabricated by the method comprises of: a first active region with a second conductive low density impurity formed in a first conductive semiconductor substrate; a second active region with a second conductive high density impurity formed in one side of said first active region; a third active region with the second conductive high density impurity formed in the other side of said first active region; a fourth active region with a first conductive high density impurity formed so as to surround said third active region; a floating gate atop a first insulating layer overlying said first active region; and a control gate atop a second insulating layer overlying said floating gate.The EEPROM cell is improved in an operational characteristic such as an erasing speed and a programming speed. The EEPROM cell is fabricated in such very small size to be integrated in a high integration degree.
    Type: Grant
    Filed: November 16, 1994
    Date of Patent: December 19, 1995
    Assignee: Goldstar Electron Co., Ltd.
    Inventor: Jung S. Goo
  • Patent number: 5328862
    Abstract: A method of making a MOSFET with a LDD structure capable of minimizing the junction capacitance and the number of manufacturing process.The method comprises the steps of forming a field oxide on a P type substrate, forming a gate oxide on the active region, forming sidewall spacers with a nitride film at side surfaces of the gate,implanting a high concentration impurity of N.sup.+ type self-aligning with the spacers as a mask to form high concentration source/drain regions of N.sup.+ type, removing the sidewall spacers,forming a thick oxide film on the active region between the field oxide and the gate,implanting a low concentration impurity of N.sup.- type and a low concentration impurity of P.sup.- type by self-aligning with the thick oxide as a mask to form low concentration source/drain regions of N.sup.- type coming into contact with high concentration source/drain regions of N.sup.+ type and to form low concentration impurity regions of P.sup.
    Type: Grant
    Filed: April 22, 1993
    Date of Patent: July 12, 1994
    Assignee: Goldstar Electron Co., Ltd.
    Inventor: Jung S. Goo