Abstract: A semiconductor device may include: a substrate having first and second surfaces; an interlayer dielectric layer having a first opening to expose the first surface; a first plug positioned in the first opening and isolated from a sidewall of the first opening by a pair of gaps; a bit line extended in any one direction while covering the first plug; a second plug including a lower part adjacent to the first plug and an upper part adjacent to the bit line, and connected to the second surface; a first air gap positioned between the first plug and the lower part of the second plug; and a second air gap positioned between the bit line and the upper part of the second plug, and having a larger width than the first air gap.

Abstract: A semiconductor device may include: a substrate having first and second surfaces; an interlayer dielectric layer having a first opening to expose the first surface; a first plug positioned in the first opening and isolated from a sidewall of the first opening by a pair of gaps; a bit line extended in any one direction while covering the first plug; a second plug including a lower part adjacent to the first plug and an upper part adjacent to the bit line, and connected to the second surface; a first air gap positioned between the first plug and the lower part of the second plug; and a second air gap positioned between the bit line and the upper part of the second plug, and having a larger width than the first air gap.

Abstract: A semiconductor device may include: a substrate having first and second surfaces; an interlayer dielectric layer having a first opening to expose the first surface; a first plug positioned in the first opening and isolated from a sidewall of the first opening by a pair of gaps; a bit line extended in any one direction while covering the first plug; a second plug including a lower part adjacent to the first plug and an upper part adjacent to the bit line, and connected to the second surface; a first air gap positioned between the first plug and the lower part of the second plug; and a second air gap positioned between the bit line and the upper part of the second plug, and having a larger width than the first air gap.

Abstract: A semiconductor device may include: a substrate having first and second surfaces; an interlayer dielectric layer having a first opening to expose the first surface; a first plug positioned in the first opening and isolated from a sidewall of the first opening by a pair of gaps; a bit line extended in any one direction while covering the first plug; a second plug including a lower part adjacent to the first plug and an upper part adjacent to the bit line, and connected to the second surface; a first air gap positioned between the first plug and the lower part of the second plug; and a second air gap positioned between the bit line and the upper part of the second plug, and having a larger width than the first air gap.

Abstract: A variable resistance memory device includes a plurality of first conductive lines extended in a first direction, a plurality of second conductive lines arranged over or under the first conductive lines and extended in a second direction crossing the first direction, an insulating layer disposed between the first conductive lines and the second conductive lines and having a trench extended in the second direction and defined by a first side wall and a second sidewall facing each other and a bottom surface connecting the first sidewall and the second sidewall, and a variable resistance material layer formed on the first and second sidewalls and the bottom surface of the trench, wherein the first and second sidewalls of the trench overlap two adjacent second conductive lines, respectively.

Abstract: A phase-change random access memory device and a method of manufacturing the same are provided. The method includes providing a semiconductor substrate including a heating electrode, forming an interlayer insulating layer including a preliminary phase-change region on the semiconductor substrate, reducing a diameter of an inlet portion of the preliminary phase-change region to be smaller than that of a bottom portion of the preliminary phase-change region, filling an insulating layer having a void in the preliminary phase-change region using a difference between the diameter of the inlet portion and the diameter of the bottom portion, removing the insulating layer to an interface between the inlet portion and the bottom portion, thereby forming a key hole exposing the heating electrode, and forming a phase-change material layer to be buried in the key hole and the preliminary phase-change region.

Abstract: A phase-change random access memory device and a method of manufacturing the same are provided. The method includes providing a semiconductor substrate including a heating electrode, forming an interlayer insulating layer including a preliminary phase-change region on the semiconductor substrate, reducing a diameter of an inlet portion of the preliminary phase-change region to be smaller than that of a bottom portion of the preliminary phase-change region, filling an insulating layer having a void in the preliminary phase-change region using a difference between the diameter of the inlet portion and the diameter of the bottom portion, removing the insulating layer to an interface between the inlet portion and the bottom portion, thereby forming a key hole exposing the heating electrode, and forming a phase-change material layer to be buried in the key hole and the preliminary phase-change region.

Abstract: A variable resistance memory device includes a plurality of first conductive lines extended in a first direction, a plurality of second conductive lines arranged over or under the first conductive lines and extended in a second direction crossing the first direction, an insulating layer disposed between the first conductive lines and the second conductive lines and having a trench extended in the second direction and defined by a first side wall and a second sidewall facing each other and a bottom surface connecting the first sidewall and the second sidewall, and a variable resistance material layer formed on the first and second sidewalls and the bottom surface of the trench, wherein the first and second sidewalls of the trench overlap two adjacent second conductive lines, respectively.

Abstract: A resistive memory device capable of minimizing operation current and a fabrication method thereof are provided. The resistive memory device includes an access device, a heating electrode formed on the access device and serving as a magnetoresistance device, and a variable resistance material formed on the heating electrode.

Abstract: A reference wafer maintains laser accuracy and calibrates a camera and a laser of a semiconductor equipment. The reference wafer includes a first anti-reflection layer, an adhesive layer, a light absorption layer and a second anti-reflection layer that are stacked over a substrate, a light reflection layer formed over the second anti-reflection layer, and a protection layer formed over the light reflection layer.

Abstract: A reference wafer maintains laser accuracy and calibrates a camera and a laser of a semiconductor equipment. The reference wafer includes a first anti-reflection layer, an adhesive layer, a light absorption layer and a second anti-reflection layer that are stacked over a substrate, a light reflection layer formed over the second anti-reflection layer, and a protection layer formed over the light reflection layer.

Abstract: A reference wafer maintains laser accuracy and calibrates a camera and a laser of a semiconductor equipment. The reference wafer includes a first anti-reflection layer, an adhesive layer, a light absorption layer and a second anti-reflection layer that are stacked over a substrate, a light reflection layer formed over the second anti-reflection layer, and a protection layer formed over the light reflection layer.

Abstract: A method for fabricating capacitor in a semiconductor device includes forming an sacrificial layer and over a substrate, forming a mask pattern over the sacrificial layer, etching the sacrificial layer in two steps with differentiated top and bottom power levels using the mask pattern as an etch mask to form an opening, and forming a bottom electrode over the opening.

Abstract: A method for fabricating a capacitor in a semiconductor device includes forming a sacrificial layer over a substrate, forming an opening by selectively etching the sacrificial layer, forming a conductive layer for a lower electrode over a whole surface of a resultant structure including the opening, forming the lower electrode by performing a first blanket dry etching process on the conductive layer until the sacrificial layer is exposed, etching the sacrificial layer to a predetermined depth to protrude a top of the lower electrode over the sacrificial layer, and performing a second blanket dry etching process on the lower electrode to remove a hornlike part on top of the lower electrode. Since a blanket dry etching is performed twice, it is possible to easily remove a hornlike part of a lower electrode and prevent a device failure induced by a micro-bridge between adjacent lower electrodes.

Abstract: The present invention relates to a semiconductor memory device and a method for fabricating the same. The semiconductor memory device, including: a plurality of gate structures formed on a substrate; a contact junction region formed beneath the substrate disposed in lateral sides of the respective gate structures; a trench formed by etching a portion of the substrate disposed in the contact junction region with a predetermined thickness; a dopant diffusion barrier layer formed on sidewalls of the trench; and a contact plug filled into a space created between the gate structures and inside of the trench, wherein the dopant diffusion barrier layer prevents dopants within the contact plug from diffusing out.

Abstract: The present invention relates to a semiconductor memory device and a method for fabricating the same. The semiconductor memory device, including: a plurality of gate structures formed on a substrate; a contact junction region formed beneath the substrate disposed in lateral sides of the respective gate structures; a trench formed by etching a portion of the substrate disposed in the contact junction region with a predetermined thickness; a dopant diffusion barrier layer formed on sidewalls of the trench; and a contact plug filled into a space created between the gate structures and inside of the trench, wherein the dopant diffusion barrier layer prevents dopants within the contact plug from diffusing out.

Abstract: A method for fabricating capacitor in a semiconductor device includes forming an sacrificial layer and over a substrate, forming a mask pattern over the sacrificial layer, etching the sacrificial layer in two steps with differentiated top and bottom power levels using the mask pattern as an etch mask to form an opening, and forming a bottom electrode over the opening.

Abstract: A method for etching platinum (Pt) includes etching a platinum layer using a gas mixture including a fluorine (F) containing gas and an inert gas. A method for fabricating a capacitor having a bottom electrode, a dielectric layer, and an upper electrode includes forming the bottom electrode by etching a platinum layer, and forming the upper electrode by etching another platinum layer, wherein the platinum layers are etched using a gas mixture including a fluorine (F) containing gas and an inert gas.

Abstract: A method for fabricating a semiconductor device is provided. The method includes: forming an inter-layer insulation layer on a substrate; forming a hard mask layer on the inter-layer insulation layer; etching the hard mask layer using a contact mask; and etching the inter-layer insulation layer using the hard mask layer as an etch barrier, thereby obtaining an opening wherein the etching of the hard mask layer and the etching of the inter-layer insulation layer are performed in one etch chamber.

Abstract: The present invention relates to a semiconductor memory device and a method for fabricating the same. The semiconductor memory device, including: a plurality of gate structures formed on a substrate; a contact junction region formed beneath the substrate disposed in lateral sides of the respective gate structures; a trench formed by etching a portion of the substrate disposed in the contact junction region with a predetermined thickness; a dopant diffusion barrier layer formed on sidewalls of the trench; and a contact plug filled into a space created between the gate structures and inside of the trench, wherein the dopant diffusion barrier layer prevents dopants within the contact plug from diffusing out.