Patents by Inventor Junichi Arita
Junichi Arita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11081438Abstract: An object of the present invention is to improve manufacturing efficiency of a semiconductor device. The method of manufacturing a semiconductor device includes a sealing step of sealing a semiconductor chip mounted on the wiring substrate. The sealing step includes a step of arranging the wiring substrate between an upper mold and a lower mold, suctioning a lower surface of the wiring substrate with the plurality of suction holes, thereby holding the wiring substrate the upper mold, and a step of sealing the semiconductor chip, an upper surface of the wiring substrate, and the plurality of side surfaces of the wiring substrate such that each of the semiconductor chip, the upper surface of the wiring substrate, and the plurality of side surfaces of the wiring substrate is covered with the resin in the lower mold.Type: GrantFiled: August 21, 2019Date of Patent: August 3, 2021Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yoshiaki Sato, Yoshinori Miyaki, Junichi Arita
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Publication number: 20200098679Abstract: An object of the present invention is to improve manufacturing efficiency of a semiconductor device. The method of manufacturing a semiconductor device includes a sealing step of sealing a semiconductor chip mounted on the wiring substrate. The sealing step includes a step of arranging the wiring substrate between an upper mold and a lower mold, suctioning a lower surface of the wiring substrate with the plurality of suction holes, thereby holding the wiring substrate the upper mold, and a step of sealing the semiconductor chip, an upper surface of the wiring substrate, and the plurality of side surfaces of the wiring substrate such that each of the semiconductor chip, the upper surface of the wiring substrate, and the plurality of side surfaces of the wiring substrate is covered with the resin in the lower mold.Type: ApplicationFiled: August 21, 2019Publication date: March 26, 2020Inventors: Yoshiaki SATO, Yoshinori MIYAKI, Junichi ARITA
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Patent number: 10098179Abstract: A compact electronic device as a constituent element of a wireless communication system using a sensor. A first feature of the device is that a first semiconductor chip is bare-chip-mounted over a front surface of a first wiring board in the form of a chip and a second semiconductor chip is bare-chip-mounted over a second wiring board in the form of a chip. A second feature is that a wireless communication unit and a data processing unit which configure a module are separately mounted. A third feature is that the first and second wiring boards are stacked in the board thickness direction to make up the module (electronic device).Type: GrantFiled: April 22, 2014Date of Patent: October 9, 2018Assignee: Renesas Electronics CorporationInventors: Shintaro Yamamichi, Hirokazu Honda, Masaki Watanabe, Junichi Arita, Norio Okada, Jun Ueno, Masashi Nishimoto, Michitaka Kimura, Tomohiro Nishiyama
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Publication number: 20140329476Abstract: A compact electronic device as a constituent element of a wireless communication system using a sensor. A first feature of the device is that a first semiconductor chip is bare-chip-mounted over a front surface of a first wiring board in the form of a chip and a second semiconductor chip is bare-chip-mounted over a second wiring board in the form of a chip. A second feature is that a wireless communication unit and a data processing unit which configure a module are separately mounted. A third feature is that the first and second wiring boards are stacked in the board thickness direction to make up the module (electronic device).Type: ApplicationFiled: April 22, 2014Publication date: November 6, 2014Applicants: RENESAS ELECTRONICS CORPORATION, RENESAS ELECTRONICS CORPORATIONInventors: Shintaro YAMAMICHI, Hirokazu HONDA, Masaki WATANABE, Junichi ARITA, Norio OKADA, Jun UENO, Masashi NISHIMOTO, Michitaka KIMURA, Tomohiro NISHIYAMA
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Patent number: 8492882Abstract: A semiconductor device has a die pad, a heat dissipating plate in the form of a frame arranged between the die pad and leads so as to surround the die pad, members that connect the die pad and the inner edge of the heat dissipating plate, and a suspension lead linked to the outer extension of the heat dissipating plate. A semiconductor chip larger than the die pad is mounted over the die pad and the members. Top surfaces of the die pad and the members in opposition to the back surface of the chip are bonded to the back surface of the chip with silver paste. Heat is conducted from the back surface of the chip to the heat dissipating plate via the silver paste, the die pad, and the members, and dissipated to the outside of the semiconductor device via the leads.Type: GrantFiled: May 4, 2012Date of Patent: July 23, 2013Assignee: Renesas Electronics CorporationInventors: Junichi Arita, Kazuko Hanawa, Makoto Nishimura
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Publication number: 20120280379Abstract: A semiconductor device has a die pad, a heat dissipating plate in the form of a frame arranged between the die pad and leads so as to surround the die pad, members that connect the die pad and the inner edge of the heat dissipating plate, and a suspension lead linked to the outer extension of the heat dissipating plate. A semiconductor chip larger than the die pad is mounted over the die pad and the members. Top surfaces of the die pad and the members in opposition to the back surface of the chip are bonded to the back surface of the chip with silver paste. Heat is conducted from the back surface of the chip to the heat dissipating plate via the silver paste, the die pad, and the members, and dissipated to the outside of the semiconductor device via the leads.Type: ApplicationFiled: May 4, 2012Publication date: November 8, 2012Inventors: JUNICHI ARITA, Kazuko Hanawa, Makoto Nishimura
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Patent number: 8188583Abstract: To improve the heat dissipation characteristics of a semiconductor device. The semiconductor device has a die pad, a heat dissipating plate in the form of a frame arranged between the die pad and a plurality of leads so as to surround the die pad, a plurality of members that connect the die pad and the inner edge of the heat dissipating plate, and a suspension lead linked to the outer extension of the heat dissipating plate, wherein a semiconductor chip the outer shape of which is larger than the die pad is mounted over the die pad and the members. The top surface of the die pad and the top surface of the members at the part in opposition to the back surface of the semiconductor chip are bonded to the back surface of the semiconductor chip in their entire surfaces with a silver paste.Type: GrantFiled: March 25, 2010Date of Patent: May 29, 2012Assignee: Renesas Electronics CorporationInventors: Junichi Arita, Kazuko Hanawa, Makoto Nishimura
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Publication number: 20100244214Abstract: To improve the heat dissipation characteristics of a semiconductor device. The semiconductor device has a die pad, a heat dissipating plate in the form of a frame arranged between the die pad and a plurality of leads so as to surround the die pad, a plurality of members that connect the die pad and the inner edge of the heat dissipating plate, and a suspension lead linked to the outer extension of the heat dissipating plate, wherein a semiconductor chip the outer shape of which is larger than the die pad is mounted over the die pad and the members. The top surface of the die pad and the top surface of the members at the part in opposition to the back surface of the semiconductor chip are bonded to the back surface of the semiconductor chip in their entire surfaces with a silver paste.Type: ApplicationFiled: March 25, 2010Publication date: September 30, 2010Inventors: Junichi ARITA, Kazuko Hanawa, Makoto Nishimura
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Publication number: 20060068046Abstract: To relieve symptoms caused by mineral deficiency such as taste abnormality and skin damage due to zinc deficiency, anemia due to iron deficiency and decreased bone mineral content due to calcium deficiency to thereby improve quality of life (QOL). Namely, foods such as foods for specific health uses and foods with nutrient function claims containing 0.1% or marc, based on gram of a dry natural plant material comprising a papaya powder etc., of zinc which are prepared by nonproliferatively stirring and/or shaking the natural plant material in a state of being suspended in a solution containing 100 ppm or greater of zinc.Type: ApplicationFiled: November 25, 2003Publication date: March 30, 2006Applicant: Junicihi AritaInventors: Junichi Arita, Yoshitane Kojima, Yutaka Yoshikawa, Munekazu Gemba, Yoshiko Kawai, Yuka Koda
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Patent number: 6774638Abstract: A highly sensitive charged particle measuring device capable of measuring low-level alpha rays comprises in a measurement chamber 7 provided with a sealable door 15, a test sample 2 and a semiconductor detector 1, a radiation measuring circuit 30 including a preamplifier 30c connected to the semiconductor detector 1, a linear amplifier 30d, and a pulse height analyzer 30e, a charged particle emission amount arithmetic unit 40 for performing the quantitative analysis of charged particles from its measurement, a display unit for displaying its analysis result, and further has an evacuation pipe line and a pure gas supply pipe line for performing supply and replacement of the pure gas in the measuring chamber 7.Type: GrantFiled: March 7, 2003Date of Patent: August 10, 2004Assignee: Hitachi, Ltd.Inventors: Nobuyoshi Kogawa, Hiroshi Kitaguchi, Tetsuya Matsui, Akihisa Kaihara, Junichi Arita
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Patent number: 6661093Abstract: For preventing &agr;-rays induced soft errors in a semiconductor device in which solder bumps are connected with Cu wirings formed on Al wirings, bump lands connected with solder bumps and Cu wirings connected integrally therewith are constituted of a stacked film of a Cu film and an Ni film formed thereon, the thickness of the stacked film is larger than the thickness of the photosensitive polyimide resin film, the thickness of the inorganic passivation film, the thickness of the third Al wiring layer and the bonding pad and the thickness of the second interlayer insulative film formed below the Cu wirings and the bump land, that is, the bump land being constituted with such a thickness as larger than any of the thickness for the insulation material and the wiring material interposed between the MISFET (n-channel MISFET and p-channel MISFET) constituting the memory cell and the bump land.Type: GrantFiled: November 20, 2001Date of Patent: December 9, 2003Assignee: Renesas Technology CorporationInventors: Kenji Ujiie, Kenichi Yamamoto, Junichi Arita
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Patent number: 6639392Abstract: A highly sensitive charged particle measuring device capable of measuring low-level alpha rays comprises in a measurement chamber 7 provided with a sealable door 15, a test sample 2 and a semiconductor detector 1, a radiation measuring circuit 30 including a preamplifier 30c connected to the semiconductor detector 1, a linear amplifier 30d, and a pulse height analyzer 30e, a charged particle emission amount arithmetic unit 40 for performing the quantitative analysis of charged particles from its measurement, a display unit for displaying its analysis result, and further has an evacuation pipe line and a pure gas supply pipe line for performing supply and replacement of the pure gas in the measuring chamber 7.Type: GrantFiled: February 28, 2002Date of Patent: October 28, 2003Assignee: Hitachi, Ltd.Inventors: Nobuyoshi Kogawa, Hiroshi Kitaguchi, Tetsuya Matsui, Akihisa Kaihara, Junichi Arita
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Patent number: 6621160Abstract: A semiconductor device in which a semiconductor chip 1 is bonded by a metal bond 2 to one surface of a heat sink 4 formed of a material with a thermal expansion coefficient is close to he semiconductor chip 1, the heat sink 4 is glued to a stiffener with a silicon adhesive 5 with an elastic modulus of 10 MPa or less, a TAB tape 9 is glued to the stiffener 3 with an epoxy adhesive 6, and the semiconductor chip 1 is sealed with an epoxy sealing resin 8 with an elastic modulus of 10 GPa or more for protection from outside.Type: GrantFiled: January 16, 2002Date of Patent: September 16, 2003Assignee: Hitachi, Ltd.Inventors: Masanori Shibamoto, Masahiro Ichitani, Ryo Haruta, Katsuyuki Matsumoto, Junichi Arita, Ichiro Anjo
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Publication number: 20030146760Abstract: A highly sensitive charged particle measuring device capable of measuring low-level alpha rays comprises in a measurement chamber 7 provided with a sealable door 15, a test sample 2 and a semiconductor detector 1, a radiation measuring circuit 30 including a preamplifier 30c connected to the semiconductor detector 1, a linear amplifier 30d, and a pulse height analyzer 30e, a charged particle emission amount arithmetic unit 40 for performing the quantitative analysis of charged particles from its measurement, a display unit for displaying its analysis result, and further has an evacuation pipe line and a pure gas supply pipe line for performing supply and replacement of the pure gas in the measuring chamber 7.Type: ApplicationFiled: March 7, 2003Publication date: August 7, 2003Applicant: Hitachi, Ltd.Inventors: Nobuyoshi Kogawa, Hiroshi Kitaguchi, Tetsuya Matsui, Akihisa Kaihara, Junichi Arita
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Patent number: 6563212Abstract: A semiconductor device in which a semiconductor chip 1 is bonded by a metal bond 2 to one surface of a heat sink 4 formed of a material with a thermal expansion coefficient is close to he semiconductor chip 1, the heat sink 4 is glued to a stiffener with a silicon adhesive 5 with an elastic modulus of 10 MPa or less, a TAB tape 9 is glued to the stiffener 3 with an epoxy adhesive 6, and the semiconductor chip 1 is sealed with an epoxy sealing resin 8 with an elastic modulus of 10 GPa or more for protection from outside.Type: GrantFiled: January 16, 2002Date of Patent: May 13, 2003Assignee: Hitachi, Ltd.Inventors: Masanori Shibamoto, Masahiro Ichitani, Ryo Haruta, Katsuyuki Matsumoto, Junichi Arita, Ichiro Anjo
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Publication number: 20030030444Abstract: A highly sensitive charged particle measuring device capable of measuring low-level alpha rays comprises in a measurement chamber 7 provided with a sealable door 15, a test sample 2 and a semiconductor detector 1, a radiation measuring circuit 30 including a preamplifier 30c connected to the semiconductor detector 1, a linear amplifier 30d, and a pulse height analyzer 30e, a charged particle emission amount arithmetic unit 40 for performing the quantitative analysis of charged particles from its measurement, a display unit for displaying its analysis result, and further has an evacuation pipe line and a pure gas supply pipe line for performing supply and replacement of the pure gas in the measuring chamber 7.Type: ApplicationFiled: February 28, 2002Publication date: February 13, 2003Applicant: Hitachi, Ltd.Inventors: Nobuyoshi Kogawa, Hiroshi Kitaguchi, Tetsuya Matsui, Akihisa Kaihara, Junichi Arita
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Publication number: 20020105070Abstract: A semiconductor device in which a semiconductor chip 1 is bonded by a metal bond 2 to one surface of a heat sink 4 formed of a material with a thermal expansion coefficient is close to he semiconductor chip 1, the heat sink 4 is glued to a stiffener with a silicon adhesive 5 with an elastic modulus of 10 MPa or less, a TAB tape 9 is glued to the stiffener 3 with an epoxy adhesive 6, and the semiconductor chip 1 is sealed with an epoxy sealing resin 8 with an elastic modulus of 10 GPa or more for protection from outside.Type: ApplicationFiled: January 16, 2002Publication date: August 8, 2002Applicant: Hitachi, Ltd.Inventors: Masanori Shibamoto, Masahiro Ichitani, Ryo Haruta, Katsuyuki Matsumoto, Junichi Arita, Ichiro Anjo
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Publication number: 20020074656Abstract: For preventing &agr;-rays induced soft errors in a semiconductor device in which solder bumps are connected with Cu wirings formed on Al wirings, bump lands connected with solder bumps and Cu wirings connected integrally therewith are constituted of a stacked film of a Cu film and an Ni film formed thereon, the thickness of the stacked film is larger than the thickness of the photosensitive polyimide resin film, the thickness of the inorganic passivation film, the thickness of the third Al wiring layer and the bonding pad and the thickness of the second interlayer insulative film formed below the Cu wirings and the bump land, that is, the bump land being constituted with such a thickness as larger than any of the thickness for the insulation material and the wiring material interposed between the MISFET (n-channel MISFET and p-channel MISFET) constituting the memory cell and the bump land.Type: ApplicationFiled: November 20, 2001Publication date: June 20, 2002Applicant: Hitachi, Ltd.Inventors: Kenji Ujiie, Kenichi Yamamoto, Junichi Arita
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Patent number: 6404049Abstract: A semiconductor device in which a semiconductor chip 1 is bonded by a metal bond 2 to one surface of a heat sink 4 formed of a material with a thermal expansion coefficient is close to the semiconductor chip 1, the heat sink 4 is glued to a stiffener with a silicon adhesive 5 with an elastic modulus of 10 MPa or less, a TAB tape 9 is glued to the stiffener 3 with an epoxy adhesive 6, and the semiconductor chip 1 is sealed with an epoxy sealing resin 8 with an elastic modulus of 10 GPa or more for protection from outside.Type: GrantFiled: May 26, 1998Date of Patent: June 11, 2002Assignee: Hitachi, Ltd.Inventors: Masanori Shibamoto, Masahiro Ichitani, Ryo Haruta, Katsuyuki Matsumoto, Junichi Arita, Ichiro Anjo
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Publication number: 20020066955Abstract: A semiconductor device in which a semiconductor chip 1 is bonded by a metal bond 2 to one surface of a heat sink 4 formed of a material with a thermal expansion coefficient is close to he semiconductor chip 1, the heat sink 4 is glued to a stiffener with a silicon adhesive 5 with an elastic modulus of 10 MPa or less, a TAB tape 9 is glued to the stiffener 3 with an epoxy adhesive 6, and the semiconductor chip 1 is sealed with an epoxy sealing resin 8 with an elastic modulus of 10 GPa or more for protection from outside.Type: ApplicationFiled: January 16, 2002Publication date: June 6, 2002Applicant: Hitachi, Ltd.Inventors: Masanori Shibamoto, Masahiro Ichitani, Ryo Haruta, Katsuyuki Matsumoto, Junichi Arita, Ichiro Anjo