Abstract: A method of forming an organic ferroelectric film configured to include an organic ferroelectric material with a crystalline property as a principal material includes (a) forming a low crystallinity film having a crystallinity lower than a crystallinity of the organic ferroelectric film on one surface of a substrate, and (b) forming the organic ferroelectric film from the low crystallinity film. The step (a) includes applying a liquid material containing the organic ferroelectric material on the one surface of the substrate and then drying the liquid material, and the step (b) includes heating and pressurizing the low crystallinity film to enhancing the crystallinity in the low crystallinity film while fairing the low crystallinity film.

Abstract: An integrated circuit device includes: a RAM block including a plurality of wordlines, a plurality of bitlines, a plurality of memory cells, and a wordline control circuit; and a data line driver block which drives a plurality of data line groups of a display panel based on data supplied from the RAM block. The data line driver block includes first to Nth (N is an integer larger than one) divided data line driver blocks, each of the first to Nth divided data line driver blocks driving a different data line group of the data line groups. The wordline control circuit drives an identical wordline N times from among the wordlines in one horizontal scan period of the display panel. The first to Nth divided data line drivers are disposed along a first direction in which the bitlines extend.

Abstract: A method for manufacturing a memory element including forming a first electrode on a first face of a substrate; forming a ferroelectric layer on a second face of the first electrode, the second face being on an opposite side to the substrate side, and the ferroelectric layer being mainly made of a crystalline organic ferroelectric material; and forming a second electrode on a third face of the ferroelectric layer, the third face being on an opposite side to the first electrode side, the second electrode being formed by ejecting an vaporized electrode material in a direction inclined with respect to a normal line direction of the substrate and depositing the vaporized electrode material on the third face of the ferroelectric layer, wherein data writing/reading is performed by changing a polarized state of the ferroelectric layer by applying a voltage between the first electrode and the second electrode.

Abstract: To provide a nondestructive-read ferroelectric memory capable of realizing high speed, high integration, and long service life. The present invention is provided with an MFSFET 100 having a ferroelectric thin film at its gate portion, word line 104, bit line 105, and bit line 106 so as to apply voltage equal to or higher than the coercive electric field of the ferroelectric thin film between the bit line 105 and the word line 104 at first write timing and apply voltage equal to or higher than the coercive electric field between the bit line 106 and the word line 104 at second write timing, and applies voltage equal to or lower than the coercive electric field of the ferroelectric thin film between the bit line 105 and the word line 104 at first read timing to detect the current flowing between the both bit lines, and applies voltage equal to or lower than the coercive electric field between the bit line 106 and the word line 104 at second read timing to detect the current flowing between the both bit lines.

Abstract: A ferroelectric material for forming a ferroelectric that is described by a general formula ABO3, includes an A-site compensation component which compensates for a vacancy of an A site, and a B-site compensation component which compensates for a vacancy of a B site.

Abstract: An integrated circuit device includes a data driver block DB, a memory block MB, and a logic circuit block LB. The data driver block DB includes a data driver DR and a buffer circuit BF which buffers a driver control signal from the logic circuit block LB and outputs the buffered driver control signal to the data driver DR. The memory block MB includes a memory cell array MA and a row address decoder RD which selects a wordline. The data driver block DB and the memory block MB are disposed along a direction D1, the buffer circuit BF and the data driver DR are disposed along a direction D2, the row address decoder RD and the memory cell array MA are disposed along the direction D2, and the buffer circuit BF and the row address decoder RD are disposed along the direction D1.

Abstract: In an integrated circuit device, a data line driver block which drives data lines of a display panel based on data supplied from a RAM block from which data is read N times (N is an integer larger than one) in one horizontal scan period 1H of the display panel includes first to N-th divided data line driver blocks disposed along a first direction in which bitlines extend. When data supplied from the RAM block is M bits (M is an integer larger than 1) and grayscale of a pixel corresponding to the data line is G bits, each of the first to N-th divided data line driver blocks includes (M/G) (multiple of three) data line driver cells which drive (M/G) data lines. (M/3G) R data line driver cells are provided in a first subdivided driver, (M/3G) G data line driver cells are provided in a second subdivided driver, and (M/3G) B data line driver cells are provided in a third subdivided driver.

Abstract: An integrated circuit device has a display memory which stores data for at least one frame displayed in a display panel which has a plurality of scan lines and a plurality of data lines, the display memory includes a plurality of RAM blocks, each of the RAM blocks including a plurality of wordlines, a plurality of bitlines, a plurality of memory cells, and a wordline control circuit, each of the RAM blocks is disposed along a first direction in which the bitlines extend, each of the memory cells has a short side and a long side, the bitlines are formed along a direction in which the long side of the memory cell extends, and the wordlines are formed along a direction in which the short side of the memory cell extends.

Abstract: An integrated circuit device includes a display memory and a data read control circuit. The data read control circuit controls data reading so that data of pixels corresponding to a plurality of signal lines is read out by N-time reading in one horizontal scan period of a display panel (N is an integer larger than 1). The display memory includes a plurality of sense amplifier cells respectively connected with a plurality of bitlines. L sense amplifier cells (L is an integer larger than 1) respectively connected with the bitlines of L memory cells adjacent in a first direction (wordline direction) in which wordlines extend are disposed along a second direction (bitline direction) in which the bitlines extend.

Abstract: An integrated circuit device has a data memory including a memory cell array which includes a plurality of wordlines, a plurality of bitlines, and a plurality of memory cells, and a memory output circuit. The data read order in the memory cell array corresponding to the arrangement of the bitlines differs from the data output order from the memory output circuit. The integrated circuit device includes a rearrangement interconnect region in a region of the memory output circuit. The rearrangement interconnect region rearranges data input in the data read order using interconnects and outputs the data in the data output order.

Abstract: An integrated circuit device includes at least one data driver block for driving data lines, a plurality of control transistors TC1 and TC2, each of the control transistors being provided corresponding to each output line of the data driver block and controlled. by using a common control signal, and a pad arrangement region in which data driver pads P1 and P2 for electrically connecting the data lines and the output lines QL1 and QL2 of the data driver block are disposed. The control transistors TC1 and TC2 are disposed in the pad arrangement region.

Abstract: Each of RAM blocks provided in a display memory and disposed along a first direction in which bitlines extend includes a sense amplifier circuit which outputs M-bit data upon one wordline selection (M is an integer larger than 1). At least M memory cells are arranged in each of the RAM blocks along a second direction in which wordlines extend. M sense amplifier cells to which M-bit data read from the M memory cells is input are provided in the sense amplifier circuit. L sense amplifier cells of the M sense amplifier cells are disposed at a position corresponding to L memory cells adjacent in the second direction (L is an integer which satisfies 2?L<M/2). When the height of the memory cell in the second direction is denoted by MCY and the height of the sense amplifier cell in the second direction is denoted by SACY, “(L?1)×MCY<SACY?L×MCY” is satisfied.

Abstract: An integrated circuit device, including first to Nth circuit blocks CB1 to CBN disposed along a first direction D1, when the first direction D1 is a direction from a first side of the integrated circuit device toward a third side which is opposite to the first side, the first side being a short side, and when a second direction D2 is a direction from a second side of the integrated circuit device toward a fourth side which is opposite to the second side, the second side being a long side. The circuit blocks CB1 to CBN include a scan driver block SB, a power supply circuit block PB, a data driver block DB, and a memory block MB. The scan driver block SB and the power supply circuit block PB are disposed adjacent to each other along the direction D1; and the data driver block DB and the memory block MB are disposed adjacent to each other along the direction D1.

Abstract: An integrated circuit device having a display memory which stores data for at least one frame from among image information displayed in a display panel which has a plurality of scan lines and a plurality of data lines, the display memory including a plurality of wordlines, a plurality of bitlines, a plurality of memory cells, and a wordline control circuit; and the wordline control circuit selecting an identical wordline N times (N is an integer larger than one) from among the wordlines in one horizontal scan period of the display panel.

Abstract: An integrated circuit device having a display memory which stores data for at least one frame from among image information displayed in a display panel which has a plurality of scan lines and a plurality of data lines, wherein the display memory includes a plurality of RAM blocks each of which includes first and second RAM block regions; wherein each of the RAM blocks includes a wordline control circuit which controls a plurality of wordlines provided in each of the first and second RAM block regions; wherein the wordline control circuit is disposed between the first and second RAM block regions; wherein the first and second RAM block regions are disposed along a first direction; and wherein the wordlines extend along the first direction.

Abstract: An integrated circuit device includes a pad PDx and an electrostatic discharge protection element ESDx formed in a rectangular region and electrically connected with the pad PDx. The pad PDx is disposed in an upper layer of the electrostatic discharge protection element ESDx so that an arrangement direction of the pads is parallel to a long side direction of the region in which the electrostatic discharge protection element ESDx is formed, and the pad PDx overlaps part or the entirety of the electrostatic discharge protection element ESDx.

Abstract: An integrated circuit device includes first to Nth circuit blocks CB1 to CBN disposed along a direction D1, a first interface region provided on the D2 side of the circuit blocks CB1 to CBN, and a second interface region provided on the D4 side of the circuit blocks CB1 to CBN. The circuit blocks CB1 to CBN include a data driver block DB and a circuit block other than the data driver block DB. When the widths of the first interface region, the circuit blocks CB1 to CBN, and the second interface region in the direction D2 are respectively W1, WB, and W2, the integrated circuit device has a width W in the direction D2 of “W1+WB+W2?W<W1+2×WB+W2”.

Abstract: An integrated circuit device includes first to Nth circuit blocks CB1 to CBN, a first interface region disposed along a fourth side and on the D2 side of the first to Nth circuit blocks CB1 to CBN, and a second interface region disposed along a second side and on the D4 side of the first to Nth circuit blocks CB1 to CBN. A local line LLG formed using a wiring layer lower than an Ith layer is provided between the adjacent circuit blocks as at least one of a signal line and a power supply line. Global lines GLG and GLD formed using the Ith or higher wiring layer are provided along the direction D1 over the circuit block disposed between the nonadjacent circuit blocks as at least one of a signal line and a power supply line.

Abstract: An integrated circuit device includes a data driver block for driving data lines. The data driver block includes a plurality of subpixel driver cells, each of which outputs a data signal corresponding to image data of one subpixel. When a direction along the long side of the subpixel driver cell is a direction D1 and a direction perpendicular to the first direction is a direction D2, the subpixel driver cells are disposed in the data driver block along the direction D1 and the direction D2. Pads are disposed on the D2 side of the data driver block. A rearrangement wiring region for rearranging the order of pull-out lines of output signals from the subpixel driver cells is provided in the arrangement region of the subpixel driver cells.

Abstract: An integrated circuit device having a display memory which stores data for at least one frame among the data displayed in a display panel which has a plurality of scan lines and a plurality of data lines. The display memory includes a plurality of wordlines, a plurality of bitlines, a plurality of memory cells, and a data read control circuit. The data read control circuit controls data reading so that data for pixels corresponding to a plurality of signal lines is read out by N times reading in one horizontal scan period of the display panel (N is an integer larger than 1).