Patents by Inventor Junichi Kasai

Junichi Kasai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11018105
    Abstract: A semiconductor device includes a semiconductor chip, a bump contract, and encapsulating layer, an insulating layer, and a connection terminal.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: May 25, 2021
    Assignee: Cypress Semiconductor Corporation
    Inventors: Masanori Onodera, Junichi Kasai
  • Publication number: 20200058610
    Abstract: A semiconductor device includes a semiconductor chip, a bump contract, and encapsulating layer, an insulating layer, and a connection terminal.
    Type: Application
    Filed: October 15, 2019
    Publication date: February 20, 2020
    Applicant: Cypress Semiconductor Corporation
    Inventors: Masanori Onodera, Junichi Kasai
  • Patent number: 10152885
    Abstract: A vehicle guidance device has a stopping vehicle detector configured to detect stopping vehicles failing to pass through a traffic light while a light is green, the traffic light being installed beside a plurality of lanes extending in a same direction, an information acquisition unit configured to acquire a starting characteristic of each detected vehicle, and a simultaneous passage line calculator configured to calculate a simultaneous passage line including a first line and a second line based on the acquired starting characteristics, when a vehicle having a lower starting characteristic than a reference starting characteristic is included in the vehicles stopping on a first lane included in the plurality of lanes, and when a vehicle having a higher starting characteristic than starting characteristics of the vehicles on the first lane is included in the vehicles stopping on a second lane included in the plurality of lanes.
    Type: Grant
    Filed: April 21, 2015
    Date of Patent: December 11, 2018
    Assignee: NISSAN MOTOR CO., LTD.
    Inventors: Seiji Shimodaira, Hiroya Fujimoto, Junichi Kasai, Yasuhisa Kishi, Satoshi Kawai
  • Publication number: 20180158330
    Abstract: A vehicle guidance device has a stopping vehicle detector configured to detect stopping vehicles failing to pass through a traffic light while a light is green, the traffic light being installed beside a plurality of lanes extending in a same direction, an information acquisition unit configured to acquire a starting characteristic of each detected vehicle, and a simultaneous passage line calculator configured to calculate a simultaneous passage line including a first line and a second line based on the acquired starting characteristics, when a vehicle having a lower starting characteristic than a reference starting characteristic is included in the vehicles stopping on a first lane included in the plurality of lanes, and when a vehicle having a higher starting characteristic than starting characteristics of the vehicles on the first lane is included in the vehicles stopping on a second lane included in the plurality of lanes.
    Type: Application
    Filed: April 21, 2015
    Publication date: June 7, 2018
    Applicant: NISSAN MOTOR CO., LTD.
    Inventors: Seiji Shimodaira, Hiroya Fujimoto, Junichi Kasai, Yasuhisa Kishi, Satoshi Kawai
  • Publication number: 20170092606
    Abstract: A semiconductor device includes a semiconductor chip, a bump contact, and encapsulating layer, an insulating layer and a connection terminal.
    Type: Application
    Filed: October 28, 2016
    Publication date: March 30, 2017
    Inventors: Masanori Onodera, Junichi Kasai
  • Patent number: 9508651
    Abstract: A semiconductor device includes a semiconductor chip, a bump electrode, a molding portion, a redistribution layer and an outer connection electrode. The bump electrode is provided on an upper face of the semiconductor chip. The molding portion encapsulates an entire side face of the semiconductor chip and seals the bump electrode so that a part of the bump electrode is exposed. The redistribution layer is provided on an upper face of the molding portion and is electrically coupled to the semiconductor chip via the bump electrode. The outer connection electrode is provided on an upper face of the redistribution layer and is electrically coupled to the bump electrode via the redistribution layer.
    Type: Grant
    Filed: February 28, 2008
    Date of Patent: November 29, 2016
    Assignee: Cypress Semiconductor Corporation
    Inventors: Masanori Onodera, Junichi Kasai
  • Patent number: 9397025
    Abstract: The present invention provides a semiconductor device including: a semiconductor chip; a lead frame provided with a recessed portion on at least one of an upper surface or a lower surface thereof, and electrically coupled to the semiconductor chip; and a resin section that molds the semiconductor chip and the lead frame, and is provided with an opening above the recessed portion. By inserting a conductive pin (not shown) into the recessed portion through the opening, a plurality of semiconductor devices can be mechanically and electrically coupled to each other.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: July 19, 2016
    Assignee: CYPRESS SEMICONDUCTOR CORPORATION
    Inventors: Kouichi Meghro, Junichi Kasai
  • Patent number: 9368424
    Abstract: A method of fabricating a semiconductor device includes the steps of providing a heat-resistant sheet on an interposer so as to cover electrode terminals provided on the interposer, and sealing a semiconductor chip on the interposer sandwiched between molds with a sealing material. The electrode terminals are covered by the heat-resistant resin for protection, and the semiconductor chip is then sealed with resin. It is thus possible to avoid the problem in which contaminations adhere to the electrode terminals. This makes it possible to prevent the occurrence of resin burrs on the interposer and contamination of the electrode pads and to improve the production yield.
    Type: Grant
    Filed: May 20, 2005
    Date of Patent: June 14, 2016
    Assignee: Cypress Semiconductor Corporation
    Inventors: Yasuhiro Shinma, Junichi Kasai, Kouichi Meguro, Masanori Onodera, Junji Tanaka
  • Patent number: 9293441
    Abstract: The present invention provides a semiconductor device that includes: stacked semiconductor chips, each semiconductor chip including a semiconductor substrate and a first insulating layer that is provided on side faces of the semiconductor substrate and has concavities formed on side faces thereof; first metal layers that are provided in center portions of inner side faces of the concavities; and second metal layers that are provided in the concavities and are connected to the first metal layers formed on each semiconductor chip. The present invention also provides a method of manufacturing the semiconductor device.
    Type: Grant
    Filed: October 4, 2011
    Date of Patent: March 22, 2016
    Assignee: CYPRESS SEMICONDUCTOR CORPORATION
    Inventors: Masataka Hoshino, Junichi Kasai, Kouichi Meguro, Ryota Fukuyama, Yasuhiro Shinma, Koji Taya, Masanori Onodera, Naomi Masuda
  • Patent number: 9142440
    Abstract: A method of producing a carrier structure for fabricating a stacked-type semiconductor device includes laminating thin plates for a lower carrier associated with an upper carrier. The method includes forming openings in the thin plates by etching or electric discharge machining. The lower carrier includes a magnet that is buried therein and the magnet maintains contact between the lower carrier and the upper carrier. A thin plate of the laminated thin plates is provided on each opposing surface of the magnet. The lower carrier further includes multiple magnets arranged around a periphery of the lower carrier and through a center region of the lower carrier that is between magnets on the periphery.
    Type: Grant
    Filed: December 3, 2008
    Date of Patent: September 22, 2015
    Assignee: Cypess Semiconductor Corporation
    Inventors: Masanori Onodera, Kouichi Meguro, Junichi Kasai, Yasuhiro Shinma, Koji Taya, Junji Tanaka
  • Publication number: 20140077347
    Abstract: The present invention provides a semiconductor device including: a semiconductor chip; a lead frame provided with a recessed portion on at least one of an upper surface or a lower surface thereof, and electrically coupled to the semiconductor chip; and a resin section that molds the semiconductor chip and the lead frame, and is provided with an opening above the recessed portion. By inserting a conductive pin (not shown) into the recessed portion through the opening, a plurality of semiconductor devices can be mechanically and electrically coupled to each other.
    Type: Application
    Filed: December 21, 2012
    Publication date: March 20, 2014
    Applicant: SPANSION LLC
    Inventors: Kouichi MEGHRO, Junichi KASAI, Masao SAKUMA
  • Patent number: 8481366
    Abstract: A semiconductor device is provided that includes a semiconductor chip and a resin section that molds the semiconductor chip and has a first through-hole. A through electrode that is electrically coupled to the semiconductor chip, extends through the resin section, and extends between a top edge and a bottom edge of an inner surface of the first through-hole. A cavity which extends between planes corresponding to an upper surface and a lower surface of the resin section is formed inside the first through-hole.
    Type: Grant
    Filed: April 26, 2011
    Date of Patent: July 9, 2013
    Assignee: Spansion LLC
    Inventors: Masahiko Harayama, Kouichi Meguro, Junichi Kasai
  • Patent number: 8421241
    Abstract: The present invention provides a semiconductor device including: a semiconductor chip; a lead frame provided with a recessed portion on at least one of an upper surface or a lower surface thereof, and electrically coupled to the semiconductor chip; and a resin section that molds the semiconductor chip and the lead frame, and is provided with an opening above the recessed portion. By inserting a conductive pin (not shown) into the recessed portion through the opening, a plurality of semiconductor devices can be mechanically and electrically coupled to each other.
    Type: Grant
    Filed: October 27, 2008
    Date of Patent: April 16, 2013
    Assignee: Spansion LLC
    Inventors: Kouichi Meghro, Junichi Kasai
  • Patent number: 8367466
    Abstract: A method in accordance with an embodiment of the invention can include forming fan-out wirings on an insulating layer formed on a wafer. Additionally, electrodes of a plurality of semiconductor chips stacked on the fan-out wirings can be electrically coupled with the fan-out wirings. The wafer can be removed.
    Type: Grant
    Filed: September 12, 2008
    Date of Patent: February 5, 2013
    Assignee: Spansion LLC
    Inventors: Masataka Hoshino, Junichi Kasai
  • Patent number: 8274158
    Abstract: Structures, methods, and systems for assessing bonding of electrodes in FCB packaging are disclosed. In one embodiment, a method comprises mounting a semiconductor chip with a plurality of first electrodes of a first shape to a mounted portion with a second electrode of a second shape, wherein the second shape is different from the first shape, bonding a respective one of the plurality of first electrodes and the second electrode using a first solder bump, generating an X-ray image of the first solder bump, and determining an acceptability of the bonding of the respective one of the plurality of first electrodes and the second electrode based on the X-ray image of the first solder bump.
    Type: Grant
    Filed: September 8, 2010
    Date of Patent: September 25, 2012
    Assignee: Spansion LLC
    Inventors: Junichi Kasai, Junji Tanaka, Naomi Masuda
  • Publication number: 20120025364
    Abstract: The present invention provides a semiconductor device that includes: stacked semiconductor chips, each semiconductor chip including a semiconductor substrate and a first insulating layer that is provided on side faces of the semiconductor substrate and has concavities formed on side faces thereof; first metal layers that are provided in center portions of inner side faces of the concavities; and second metal layers that are provided in the concavities and are connected to the first metal layers formed on each semiconductor chip. The present invention also provides a method of manufacturing the semiconductor device.
    Type: Application
    Filed: October 4, 2011
    Publication date: February 2, 2012
    Inventors: Masataka HOSHINO, Junichi KASAI, Kouichi MEGURO, Ryota FUKUYAMA, Yasuhiro SHINMA, Koji TAYA, Masanori ONODERA, Naomi MASUDA
  • Patent number: 8039943
    Abstract: A semiconductor device is provided that includes a semiconductor chip and a resin section that molds the semiconductor chip and has a first through-hole. A through electrode that is electrically coupled to the semiconductor chip, extends through the resin section, and extends between a top edge and a bottom edge of an inner surface of the first through-hole. A cavity which extends between planes corresponding to an upper surface and a lower surface of the resin section is formed inside the first through-hole.
    Type: Grant
    Filed: September 26, 2008
    Date of Patent: October 18, 2011
    Assignee: Spansion, LLC
    Inventors: Masahiko Harayama, Kouichi Meguro, Junichi Kasai
  • Patent number: 8030179
    Abstract: The present invention provides a semiconductor device that includes: stacked semiconductor chips, each semiconductor chip including a semiconductor substrate and a first insulating layer that is provided on side faces of the semiconductor substrate and has concavities formed on side faces thereof; first metal layers that are provided in center portions of inner side faces of the concavities; and second metal layers that are provided in the concavities and are connected to the first metal layers formed on each semiconductor chip. The present invention also provides a method of manufacturing the semiconductor device.
    Type: Grant
    Filed: September 9, 2009
    Date of Patent: October 4, 2011
    Assignee: Spansion, LLC
    Inventors: Masataka Hoshino, Junichi Kasai, Kouichi Meguro, Ryota Fukuyama, Yasuhiro Shinma, Koji Taya, Masanori Onodera, Naomi Masuda
  • Publication number: 20110201152
    Abstract: A semiconductor device is provided that includes a semiconductor chip and a resin section that molds the semiconductor chip and has a first through-hole. A through electrode that is electrically coupled to the semiconductor chip, extends through the resin section, and extends between a top edge and a bottom edge of an inner surface of the first through-hole. A cavity which extends between planes corresponding to an upper surface and a lower surface of the resin section is formed inside the first through-hole.
    Type: Application
    Filed: April 26, 2011
    Publication date: August 18, 2011
    Inventors: Masahiko HARAYAMA, Kouichi MEGURO, Junichi KASAI
  • Patent number: 7968990
    Abstract: A method of fabricating a semiconductor device includes: mounting a semiconductor chip on a substrate; forming an upper connection terminal on a side of the substrate on which the semiconductor chip is mounted; forming a resin seal portion that seals the semiconductor chip and the upper connection terminal so that an upper surface of the upper connection terminal is exposed; and shaping the upper connection terminal so that the upper surface of the upper connection terminal becomes lower than an upper surface of the resin seal portion.
    Type: Grant
    Filed: January 17, 2007
    Date of Patent: June 28, 2011
    Assignee: Spansion LLC
    Inventors: Junji Tanaka, Junichi Kasai, Kouichi Meguro, Masanori Onodera, Koji Taya