Patents by Inventor Junichi Sato

Junichi Sato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Mutated genes for the catalytic protein of oplophorus luciferase and use thereof
    Patent number: 10907134
    Abstract: Luciferases which are different from those known heretofore have been desired. A luciferase mutant comprising an amino acid sequence in which at least one amino acid selected from the group consisting of valine at the position of 44, alanine at the position of 54 and tyrosine at the position of 138 is substituted with other amino acid(s) in the amino acid sequence of SEQ ID NO: 2.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: February 2, 2021
    Assignee: JNC CORPORATION
    Inventors: Satoshi Inouye, Junichi Sato
  • SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM
    Publication number: 20210005272
    Abstract: A semiconductor memory device includes: a memory cell array; a peripheral circuit connected to this memory cell array, the peripheral circuit outputting data in the memory cell array as a read data in response to input of a command set, the command set including a first command, address data, and a second command; a first electrode capable of being used in input of the command set and output of the read data; and a second electrode capable of supplying electric power to the peripheral circuit. A current flowing in the second electrode at a second timing is larger than a current flowing in the second electrode at a first timing, the first timing being a timing at which the first command is inputted, the second timing being a timing before which the input of the address data is started and after which an input of the second command is finished.
    Type: Application
    Filed: September 17, 2020
    Publication date: January 7, 2021
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Yuuta SANO, Junichi SATO
  • SEMICONDUCTOR STORAGE DEVICE AND MEMORY SYSTEM
    Publication number: 20200402550
    Abstract: A semiconductor storage device includes a sense amplifier configured to read and program data in memory cells, a first latch circuit to store read data or program data, a second latch circuit to store the first data transferred from the first latch circuit or the second data before the second data is transferred into the first latch circuit, an input/output circuit to output the first data stored in the second latch circuit and to transfer the second data received thereby to the second latch circuit, and a control circuit. Upon receiving a read command while the control circuit is performing a program operation on program data stored in second latch circuit, the control circuit interrupts the program operation to perform the read operation and resumes the program operation on the program data in response to a resume write command sequence that does not include the program data.
    Type: Application
    Filed: August 5, 2020
    Publication date: December 24, 2020
    Inventors: Junichi SATO, Akio SUGAHARA
  • WATCH PART
    Publication number: 20200362438
    Abstract: A watch part containing a titanium alloy, the titanium alloy, in mass %, includes: Al: 1.0 to 3.5%; Fe: 0.1 to 0.4%; 0: 0.00 to 0.15%; C: 0.00 to 0.10%; Sn: 0.00 to 0.20%; Si: 0.00 to 0.15%; and the balance: Ti and impurities, an average grain diameter of ? phase crystal grains is 15.0 ?m or less, an average aspect ratio of the ? phase crystal grains is 1.0 or more and 3.0 or less, and a coefficient of variation of a number density of ?-phase crystal grains distributed in the ? phase is 0.30 or less.
    Type: Application
    Filed: August 28, 2018
    Publication date: November 19, 2020
    Applicants: NIPPON STEEL CORPORATION, CASIO COMPUTER CO., LTD.
    Inventors: Genki TSUKAMOTO, Kazuhiro TAKAHASHI, Hideto SETO, Naoki OKAMURA, Junichi SATO
  • Semiconductor memory device and memory system
    Patent number: 10811108
    Abstract: A semiconductor memory device includes: a memory cell array; a peripheral circuit connected to this memory cell array, the peripheral circuit outputting data in the memory cell array as a read data in response to input of a command set, the command set including a first command, address data, and a second command; a first electrode capable of being used in input of the command set and output of the read data; and a second electrode capable of supplying electric power to the peripheral circuit. A current flowing in the second electrode at a second timing is larger than a current flowing in the second electrode at a first timing, the first timing being a timing at which the first command is inputted, the second timing being a timing before which the input of the address data is started and after which an input of the second command is finished.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: October 20, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yuuta Sano, Junichi Sato
  • Semiconductor storage device and memory system
    Patent number: 10777239
    Abstract: A semiconductor storage device includes a sense amplifier configured to read and program data in memory cells, a first latch circuit to store read data or program data, a second latch circuit to store the first data transferred from the first latch circuit or the second data before the second data is transferred into the first latch circuit, an input/output circuit to output the first data stored in the second latch circuit and to transfer the second data received thereby to the second latch circuit, and a control circuit. Upon receiving a read command while the control circuit is performing a program operation on program data stored in second latch circuit, the control circuit interrupts the program operation to perform the read operation and resumes the program operation on the program data in response to a resume write command sequence that does not include the program data.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: September 15, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Junichi Sato, Akio Sugahara
  • REFLOW ENDURANCE IMPROVEMENTS IN TRIPLE-LEVEL CELL NAND FLASH
    Publication number: 20200272363
    Abstract: Disclosed is a memory device and method of operating the same. In one embodiment, a method is disclosed comprising generating compressed data by compressing raw data for storage in a memory device, pre-programming a first region of the memory device with the compressed data, and, in response to detecting that the memory device has powered on, decompressing the compressed data, obtaining the raw data, and transferring the raw data to a second region of the memory device.
    Type: Application
    Filed: February 21, 2019
    Publication date: August 27, 2020
    Inventor: Junichi Sato
  • MEMORY DEVICE
    Publication number: 20200202958
    Abstract: According one embodiment, a memory device includes: a memory cell array; a voltage generation circuit generating one or more voltages supplied to the memory cell array; an input/output circuit receiving an address indicating a region in the memory cell array; and a control circuit controlling operations of the memory cell array. The voltage generation circuit generates the voltages during reception of the address.
    Type: Application
    Filed: September 11, 2019
    Publication date: June 25, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Akio SUGAHARA, Takaya HANDA, Ryosuke ISOMURA, Kazuto UEHARA, Junichi SATO, Norichika ASAOKA, Masashi YAMAOKA, Bushnaq SANAD, Yuzuru SHIBAZAKI, Noriyasu KUMAZAKI, Yuri TERADA
  • SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM
    Publication number: 20200185043
    Abstract: A semiconductor memory device includes: a memory cell array; a peripheral circuit connected to this memory cell array, the peripheral circuit outputting data in the memory cell array as a read data in response to input of a command set, the command set including a first command, address data, and a second command; a first electrode capable of being used in input of the command set and output of the read data; and a second electrode capable of supplying electric power to the peripheral circuit. A current flowing in the second electrode at a second timing is larger than a current flowing in the second electrode at a first timing, the first timing being a timing at which the first command is inputted, the second timing being a timing before which the input of the address data is started and after which an input of the second command is finished.
    Type: Application
    Filed: August 9, 2019
    Publication date: June 11, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Yuuta SANO, Junichi SATO
  • Outdoor terminal device
    Patent number: 10679454
    Abstract: An outdoor terminal device is provided such that after performing an operation on a display with a touch panel, a user can perform an action associated with the operation by moving a hand without being hindered. The outdoor terminal device is equipped with a door having a display with a touch panel on a front surface of a case, and multiple internal units are housed inside the case. The door has panels in predetermined areas. The predetermined areas refer to areas excluding the display area and a function-securing area. An operation surface of the display with a touch panel and front surfaces of the panels are disposed on the same plane in a depth direction. No protruding object is present in a front surface area of the panels located between the operation surface of the display with a touch panel and the function-securing area disposed on an end part of the panels.
    Type: Grant
    Filed: August 17, 2016
    Date of Patent: June 9, 2020
    Assignee: NEC Platforms, Ltd.
    Inventor: Junichi Sato
  • SOUND GENERATOR FOR VEHICLE
    Publication number: 20200154211
    Abstract: A sound generator for a vehicle includes a sounder, a housing surrounding the sounder, a connector unit, a connecting terminal. The sounder includes a diaphragm, a voice coil connected to the diaphragm, and a lead wire extending from the voice coil. The connector unit includes an opening facing toward outside the housing. A vehicle connector is configured to be mounted on the connector unit to electrically connect the connector unit with a device in the vehicle. The connecting terminal is located to protrude inward the housing from the opening of the connector unit. The lead wire extending from the voice coil is directly connected to the connecting terminal in the housing.
    Type: Application
    Filed: January 20, 2020
    Publication date: May 14, 2020
    Inventors: Susumu MIYATA, Junichi SATO
  • REAL-TIME SELECTION OF DATA TO COLLECT IN AUTONOMOUS VEHICLE
    Publication number: 20200118359
    Abstract: A method for an autonomous vehicle includes: controlling at least one system of the vehicle by a host system; monitoring, by a memory device, data associated with operation of the vehicle; determining, by the memory device based on the monitoring, first data to collect from the vehicle; collecting, by the memory device independently of the host system, the first data; and storing, by the memory device, the collected first data in a non-volatile memory.
    Type: Application
    Filed: October 10, 2018
    Publication date: April 16, 2020
    Inventor: Junichi Sato
  • AUTOMATIC COLLECTION OF AUTONOMOUS VEHICLE LOGGING DATA
    Publication number: 20200111270
    Abstract: A method for an autonomous vehicle includes: controlling at least one system of the vehicle by a host system; automatically collecting, by a memory device, data generated by the at least one system, where the data is collected by the memory device independently of control by the host system; and storing the data in the memory device.
    Type: Application
    Filed: October 3, 2018
    Publication date: April 9, 2020
    Inventor: Junichi Sato
  • SUBSTRATE PROCESSING APPARATUS AND PURGING METHOD
    Publication number: 20200083078
    Abstract: A substrate processing apparatus includes: a carrier storage rack configured to place and store a carrier that accommodates a substrate; a gas supply configured to supply an inert gas into the carrier placed on the carrier storage rack; and a controller configured to control whether to supply the inert gas into the carrier based on at least one of carrier information and substrate information.
    Type: Application
    Filed: August 23, 2019
    Publication date: March 12, 2020
    Inventors: Moriyoshi Kinoshita, Yuji Sasaki, Junichi Sato, Takashi Asakawa
  • MUTATED GENES FOR THE CATALYTIC PROTEIN OF OPLOPHORUS LUCIFERASE AND USE THEREOF
    Publication number: 20200056162
    Abstract: Luciferases which are different from those known heretofore have been desired. A luciferase mutant comprising an amino acid sequence in which at least one amino acid selected from the group consisting of valine at the position of 44, alanine at the position of 54 and tyrosine at the position of 138 is substituted with other amino acid(s) in the amino acid sequence of SEQ ID NO: 2.
    Type: Application
    Filed: October 30, 2019
    Publication date: February 20, 2020
    Applicant: JNC CORPORATION
    Inventors: Satoshi INOUYE, Junichi SATO
  • Mutated genes for the catalytic protein of oplophorus luciferase and use thereof
    Patent number: 10519428
    Abstract: Luciferases which are different from those known heretofore have been desired. A luciferase mutant comprising an amino acid sequence in which at least one amino acid selected from the group consisting of valine at the position of 44, alanine at the position of 54 and tyrosine at the position of 138 is substituted with other amino acid(s) in the amino acid sequence of SEQ ID NO: 2.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: December 31, 2019
    Assignee: JNC CORPORATION
    Inventors: Satoshi Inouye, Junichi Sato
  • DOWNLOADING SYSTEM MEMORY DATA IN RESPONSE TO EVENT DETECTION
    Publication number: 20190385383
    Abstract: A method includes detecting an event occurring on a vehicle. The vehicle includes at least one computing device that controls at least one operation of the vehicle. The at least one computing device includes a first computing device comprising system memory. In response to detecting the event, data is downloaded from the system memory to a non-volatile memory device of the vehicle. In some cases, a control action for the vehicle is implemented based on analysis of the downloaded data.
    Type: Application
    Filed: June 18, 2018
    Publication date: December 19, 2019
    Inventor: Junichi Sato
  • Non-volatile semiconductor storage device with two write modes
    Patent number: 10504598
    Abstract: A non-volatile semiconductor storage device includes a memory cell array and a control circuit configured to control a data write operation for the memory cell array in a first or second write mode in response to a write command sequence. In the first write mode, the control circuit performs a first write operation, which includes an operation in which one or more bit lines are charged according to write data and an operation in which a write voltage is applied to a selected word line according to address data included in the write command sequence. In the second write mode, the control circuit performs a second write operation, which includes the operation in which the one or more bit lines are charged according to the write data and does not include the operation in which the write voltage is applied to the selected word line.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: December 10, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Kazuto Uehara, Yoshikazu Harada, Kenta Shibasaki, Junichi Sato, Akio Sugahara
  • SEMICONDUCTOR STORAGE DEVICE AND MEMORY SYSTEM
    Publication number: 20190362761
    Abstract: A semiconductor storage device includes a sense amplifier configured to read and program data in memory cells, a first latch circuit to store read data or program data, a second latch circuit to store the first data transferred from the first latch circuit or the second data before the second data is transferred into the first latch circuit, an input/output circuit to output the first data stored in the second latch circuit and to transfer the second data received thereby to the second latch circuit, and a control circuit. Upon receiving a read command while the control circuit is performing a program operation on program data stored in second latch circuit, the control circuit interrupts the program operation to perform the read operation and resumes the program operation on the program data in response to a resume write command sequence that does not include the program data.
    Type: Application
    Filed: August 29, 2018
    Publication date: November 28, 2019
    Inventors: Junichi SATO, Akio SUGAHARA
  • Connection structure, magnetic annealing device using same, and connecting method
    Patent number: 10473399
    Abstract: Disclosed is a connection structure that connects a housing to a magnetic annealing furnace that is provided with a fixedly arranged magnet and includes a first drum flange having a cylindrical flange portion. The connection structure includes: a second drum flange that is attached and fixed to the housing and includes a flange portion configured to externally or internally fit the flange portion of the first drum flange thereto; a first sealant that is installed between facing surfaces of the housing and the second drum flange; and a second sealant that is installed between facing surfaces of the first and second drum flanges.
    Type: Grant
    Filed: January 20, 2016
    Date of Patent: November 12, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Ian Colgan, George Eyres, Ioan Domsa, Junichi Sato, Koyu Hasegawa, Tomoaki Abe