Abstract: The output of a tri-state driver is connected with I/O pins of test IC elements via load resistors. The I/O pins are connected to the input terminals of corresponding comparators. Under the state where the I/O control signal given to the driver indicates an input condition, the driver generates either the first or the second level corresponding to the logic level of input test pattern data. Under the state where the I/O control signal indicates an output condition, the driver generates the third level which is different from the first and the second level.

Abstract: In a memory tester in which data read out of an address of a memory under test, specified by a pattern generator, is compared with an expected value and the result of comparison is written into a failure analysis memory at the address corresponding to that of the memory under test from which the data was read out, the output address of an address pointer which is incremented or decremented upon each application of a clock and the address from the pattern generator are selectively applied to the failure analysis memory. In the case of testing a memory which has an internal address generating function, the address from the address pointer is provided to the failure analysis memory.

Abstract: Supplied with an output response signal from a circuit under test in each test channel, a level comparator compares the signal with a reference level which defines a normal logical level. The compared output is applied to two independent signal detectors, wherein it is detected and held at the timing of two strobe pulses which are provided thereto via two different signal lines at a desired time interval. These detected signals are applied to two logical comparators, wherein they are compared with expected value signals, respectively. An expected value signal switching circuit may be provided by which the expected value signal in this test channel and the expected value signal in another test channel are selectively provided to one of the logical comparators. It is also possible to adopt an arrangement in which test results read out of a plurality of storage areas of a failure analysis memory are provided as mask data to a desired one of the logical comparators to thereby mask its logical comparison.

Abstract: In a semiconductor test system, higher accuracy testing of semiconductor memories is achieved by providing test data from a modified pattern generator to identical addresses in both the memory under test and a buffer memory. This is achieved for various types of semiconductor memories by treating data generated by the modified pattern generator for the memory under tests in ways that would correspond to how the data is treated in various memories to be tested before storing the data in the buffer memory. This is accomplished using a variety of multiplexers and counters under control of a control signal generator. Data stored at locations with the same address in both memories is read out for comparison in a logic comparator. If the data is not identical, the semiconductor memory under test is rejected as defective.

Abstract: A counter counts clock signals following a reference signal to provide an address for accessing a memory wherein marks are stored at respective addresses corresponding to desired timing signals with respect to the reference signal. The memory has plural channels, all of which are accessed by the same count value, to provide different timing signals on different channel outputs corresponding to the marks stored in respective portions of the memory. Different sets of timing signals can be stored in different memory blocks, and the memory block which is accessed by the count value can be selected. The memory can be divided into plural memories of smaller capacity, and low speed memories can be used. A timing signal with respect to a first reference signal can be provided after the occurrence of the subsequent reference signal.

Abstract: A system for testing logical devices, in which a pattern file is used to store numerous test patterns, each of which includes both an input pattern, which is provided as an input to the device under test, and an expected value pattern, which is compared with the actual output of the device under test to ascertain whether malfunction has occurred. By accessing the pattern file at various addresses, different test patterns can selectively be applied to the device in a test. A command file includes instructions for controlling the sequence in which the various test patterns included in the pattern file are accessed, and an operand file includes data which may be required for carrying out the instructions contained in the command file. Index, stack point, and subroutine return registers are also used to execute the instructions which may be contained in the command file.