Patents by Inventor Junko Izumitani
Junko Izumitani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11587738Abstract: A capacitor that includes a substrate, a lower electrode on the substrate, a dielectric film on the lower electrode, an upper electrode on a part of the dielectric film, a protective layer that covers the lower electrode and the upper electrode, and an external electrode that penetrates the protective layer. The external electrode is formed only in a region defined by a periphery of the upper electrode in a plan view of the capacitor viewed from an upper surface thereof towards the substrate.Type: GrantFiled: November 29, 2021Date of Patent: February 21, 2023Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Masatomi Harada, Junko Izumitani, Takeshi Kagawa, Hiroshi Matsubara
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Patent number: 11521800Abstract: A capacitor that includes a substrate having a first principal surface and a second principal surface, a lower electrode on the first principal surface, a dielectric film on the lower electrode, and an upper electrode on the dielectric film, wherein at least one of the lower electrode and the upper electrode has, in plan view of the first principal surface, a first region having a rectangular shape, and at least one second region protruding from at least one side of the first region.Type: GrantFiled: April 16, 2019Date of Patent: December 6, 2022Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Takeshi Kagawa, Junko Izumitani, Masatomi Harada, Nobuhiro Ishida
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Patent number: 11476055Abstract: A capacitor that includes a lower electrode; a dielectric film; an upper electrode; a first protective film that has a first through hole that opens to the upper electrode and a second through hole that opens to the lower electrode, and has a first upper surface; a second protective film that has a second upper surface located higher than the first upper surface of the first protective film; a first terminal electrode electrically connected to the upper electrode through the first through hole, and extends to at least the second upper surface of the second protective film; and a second terminal electrode electrically connected to the lower electrode through the second through hole, and extends to at least the second upper surface of the second protective film.Type: GrantFiled: November 13, 2019Date of Patent: October 18, 2022Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Takeshi Kagawa, Junko Izumitani, Masatomi Harada, Hiroshi Matsubara, Nobuhiro Ishida
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Patent number: 11474063Abstract: A semiconductor device that includes a semiconductor substrate having a first main surface and a second main surface opposed to each other, and a porous metal oxide film on a side of the first main surface of the semiconductor substrate, the porous metal oxide film having a plurality of pores. The semiconductor substrate has a connection electrically connected to the porous metal oxide film, and the semiconductor substrate is configured to provide a power supply path from the second main surface to the connection on the first main surface.Type: GrantFiled: April 17, 2020Date of Patent: October 18, 2022Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Hiroshi Matsubara, Junko Izumitani, Hideaki Ooe, Masutaro Nemoto
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Publication number: 20220084754Abstract: A capacitor that includes a substrate, a lower electrode on the substrate, a dielectric film on the lower electrode, an upper electrode on a part of the dielectric film, a protective layer that covers the lower electrode and the upper electrode, and an external electrode that penetrates the protective layer. The external electrode is formed only in a region defined by a periphery of the upper electrode in a plan view of the capacitor viewed from an upper surface thereof towards the substrate.Type: ApplicationFiled: November 29, 2021Publication date: March 17, 2022Inventors: Masatomi Harada, Junko Izumitani, Takeshi Kagawa, Hiroshi Matsubara
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Patent number: 11232911Abstract: A capacitor that includes a substrate having a first principal surface, a second principal surface facing the first principal surface, and a first end surface connecting the first principal surface and the second principal surface, a lower electrode on the first principal surface of the substrate, a dielectric film on the lower electrode, an upper electrode on the dielectric film, a protective film covering the upper electrode and having a thickness smaller than that of the substrate, and a first terminal electrode on the first end surface and electrically connected to one of the upper electrode and the lower electrode.Type: GrantFiled: April 17, 2019Date of Patent: January 25, 2022Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Nobuhiro Ishida, Junko Izumitani, Masatomi Harada, Takeshi Kagawa
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Patent number: 11217395Abstract: A capacitor that includes a substrate, a lower electrode on the substrate, a dielectric film on the lower electrode, an upper electrode on a part of the dielectric film, a protective layer that covers the lower electrode and the upper electrode, and an external electrode that penetrates the protective layer. The external electrode is formed only in a region defined by a periphery of the upper electrode in a plan view of the capacitor viewed from an upper surface thereof towards the substrate.Type: GrantFiled: June 21, 2019Date of Patent: January 4, 2022Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Masatomi Harada, Junko Izumitani, Takeshi Kagawa, Hiroshi Matsubara
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Patent number: 11101072Abstract: A capacitor that prevents generation of a substrate capacitance composed of an upper electrode, a substrate, and a lower electrode. Specifically, the capacitor includes a substrate; a lower electrode disposed on the substrate; a dielectric film disposed on the lower electrode; an upper electrode disposed on a part of the dielectric film; and a first terminal electrode that is connected to the upper electrode. Moreover, the upper electrode and the first terminal electrode are formed in a region for forming the lower electrode in a plan view of the capacitor viewed from the first terminal electrode side.Type: GrantFiled: December 17, 2018Date of Patent: August 24, 2021Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Masatomi Harada, Junko Izumitani, Takeshi Kagawa, Nobuhiro Ishida
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Patent number: 11011548Abstract: An electronic device includes a plurality of layers formed on a silicon-on-insulator (SOI) substrate. The SOI substrate includes a support substrate, a buried insulating layer formed on the support substrate, and a silicon layer formed on the buried insulating layer. A membrane structure of the electronic device includes the plurality of layers, the buried insulating later and the silicon layer but does not include the support substrate. A passivation film covers an upper surface and a side surface of the membrane structure.Type: GrantFiled: April 30, 2019Date of Patent: May 18, 2021Assignee: MURATA MANUFACTURING CO., LTD.Inventor: Junko Izumitani
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Publication number: 20200249188Abstract: A semiconductor device that includes a semiconductor substrate having a first main surface and a second main surface opposed to each other, and a porous metal oxide film on a side of the first main surface of the semiconductor substrate, the porous metal oxide film having a plurality of pores. The semiconductor substrate has a connection electrically connected to the porous metal oxide film, and the semiconductor substrate is configured to provide a power supply path from the second main surface to the connection on the first main surface.Type: ApplicationFiled: April 17, 2020Publication date: August 6, 2020Inventors: Hiroshi Matsubara, Junko Izumitani, Hideaki Ooe, Masutaro Nemoto
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Publication number: 20200082989Abstract: A capacitor that includes a lower electrode; a dielectric film; an upper electrode; a first protective film that has a first through hole that opens to the upper electrode and a second through hole that opens to the lower electrode, and has a first upper surface; a second protective film that has a second upper surface located higher than the first upper surface of the first protective film; a first terminal electrode electrically connected to the upper electrode through the first through hole, and extends to at least the second upper surface of the second protective film; and a second terminal electrode electrically connected to the lower electrode through the second through hole, and extends to at least the second upper surface of the second protective film.Type: ApplicationFiled: November 13, 2019Publication date: March 12, 2020Inventors: Takeshi Kagawa, Junko Izumitani, Masatomi Harada, Hiroshi Matsubara, Nubuhiro Ishida
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Publication number: 20190311854Abstract: A capacitor that includes a substrate, a lower electrode on the substrate, a dielectric film on the lower electrode, an upper electrode on a part of the dielectric film, a protective layer that covers the lower electrode and the upper electrode, and an external electrode that penetrates the protective layer. The external electrode is formed only in a region defined by a periphery of the upper electrode in a plan view of the capacitor viewed from an upper surface thereof towards the substrate.Type: ApplicationFiled: June 21, 2019Publication date: October 10, 2019Inventors: Masatomi Harada, Junko Izumitani, Takeshi Kagawa, Hiroshi Matsubara
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Publication number: 20190259779Abstract: An electronic device includes a plurality of layers formed on a silicon-on-insulator (SOI) substrate. The SOI substrate includes a support substrate, a buried insulating layer formed on the support substrate, and a silicon layer formed on the buried insulating layer. A membrane structure of the electronic device includes the plurality of layers, the buried insulating later and the silicon layer but does not include the support substrate. A passivation film covers an upper surface and a side surface of the membrane structure.Type: ApplicationFiled: April 30, 2019Publication date: August 22, 2019Inventor: Junko Izumitani
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Publication number: 20190244762Abstract: A capacitor that includes a substrate having a first principal surface, a second principal surface facing the first principal surface, and a first end surface connecting the first principal surface and the second principal surface, a lower electrode on the first principal surface of the substrate, a dielectric film on the lower electrode, an upper electrode on the dielectric film, a protective film covering the upper electrode and having a thickness smaller than that of the substrate, and a first terminal electrode on the first end surface and electrically connected to one of the upper electrode and the lower electrode.Type: ApplicationFiled: April 17, 2019Publication date: August 8, 2019Inventors: Nobuhiro Ishida, Junko Izumitani, Masatomi Harada, Takeshi Kagawa
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Publication number: 20190244761Abstract: A capacitor that includes a substrate having a first principal surface and a second principal surface, a lower electrode on the first principal surface, a dielectric film on the lower electrode, and an upper electrode on the dielectric film, wherein at least one of the lower electrode and the upper electrode has, in plan view of the first principal surface, a first region having a rectangular shape, and at least one second region protruding from at least one side of the first region.Type: ApplicationFiled: April 16, 2019Publication date: August 8, 2019Inventors: Takeshi Kagawa, Junko Izumitani, Masatomi Harada, Nobuhiro Ishida
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Publication number: 20190122820Abstract: A capacitor that prevents generation of a substrate capacitance composed of an upper electrode, a substrate, and a lower electrode. Specifically, the capacitor includes a substrate; a lower electrode disposed on the substrate; a dielectric film disposed on the lower electrode; an upper electrode disposed on a part of the dielectric film; and a first terminal electrode that is connected to the upper electrode. Moreover, the upper electrode and the first terminal electrode are formed in a region for forming the lower electrode in a plan view of the capacitor viewed from the first terminal electrode side.Type: ApplicationFiled: December 17, 2018Publication date: April 25, 2019Inventors: Masatomi Harada, Junko Izumitani, Takeshi Kagawa, Nobuhiro Ishida
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Publication number: 20190074348Abstract: A capacitor that includes a substrate; a lower electrode formed on the substrate, and including an upper surface, a lower surface and an end surface that connects the upper surface and the lower surface. Moreover, the capacitor includes a dielectric film formed on the lower electrode; an upper electrode formed on the dielectric film; and a terminal electrode connected to the upper electrode. Furthermore, the upper surface of the lower electrode is formed in a region on an inner side of a periphery of the lower surface of the lower electrode with at least part of the end surface being a tapered shape.Type: ApplicationFiled: November 5, 2018Publication date: March 7, 2019Inventors: Nobuhiro Ishida, Junko Izumitani, Masatomi Harada, Takeshi Kagawa
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Patent number: 10177289Abstract: A mounting substrate that includes external connection electrodes on a rear surface of a base material, and mounting electrodes on a front surface of the base material. In-hole electrodes connect the external connection electrodes and the mounting electrodes. A reflective film containing Al is located between the base material and the mounting electrodes. The reflective film is covered with an insulating film layer.Type: GrantFiled: April 7, 2017Date of Patent: January 8, 2019Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Yuki Fukui, Junko Izumitani, Tadayuki Okawa
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Patent number: 8008730Abstract: To provide a manufacturing method of a semiconductor device which can improve the reliability of the semiconductor device. A first insulating film for covering a semiconductor element formed in a semiconductor substrate is formed by a thermal CVD method or the like which has a good embedding property. A second insulating film is formed to cover the first insulating film by a plasma CVD method which has excellent humidity resistance. A plug is formed to penetrate the first insulating film and the second insulating film. A third insulating film comprised of a low-k film having a relatively low dielectric constant is formed over the second insulating film. A wiring is formed in the third insulating film by a damascene technique to be electrically coupled to the plug.Type: GrantFiled: July 13, 2009Date of Patent: August 30, 2011Assignee: Renesas Electronics CorporationInventors: Shoichi Fukui, Noboru Morimoto, Yasutaka Nishioka, Junko Izumitani, Atsushi Ishii
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Publication number: 20100052062Abstract: To provide a manufacturing method of a semiconductor device which can improve the reliability of the semiconductor device. A first insulating film for covering a semiconductor element formed in a semiconductor substrate is formed by a thermal CVD method or the like which has a good embedding property. A second insulating film is formed to cover the first insulating film by a plasma CVD method which has excellent humidity resistance. A plug is formed to penetrate the first insulating film and the second insulating film. A third insulating film comprised of a low-k film having a relatively low dielectric constant is formed over the second insulating film. A wiring is formed in the third insulating film by a damascene technique to be electrically coupled to the plug.Type: ApplicationFiled: July 13, 2009Publication date: March 4, 2010Inventors: Shoichi Fukui, Noboru Morimoto, Yasutaka Nishioka, Junko Izumitani, Atsushi Ishii