Patents by Inventor Juraj Vavro

Juraj Vavro has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220302286
    Abstract: In an example, a semiconductor device includes a cathode region having a first conductivity type and a cathode region dopant concentration. A charge storage region overlies the cathode region and has the first conductivity type and a charge storage region dopant concentration less than the cathode region dopant concentration. A buffer region overlies the charge storage region and has the first conductivity type, a buffer region thickness, a buffer region dopant concentration profile, and a buffer region peak dopant concentration. A drift region overlies the buffer region and has the first conductivity type and a drift region dopant concentration. An anode region of a second conductivity type opposite to the first conductivity type is adjacent to the drift region. The buffer region peak dopant concentration is greater than the charge storage region dopant concentration and greater than the drift region dopant concentration.
    Type: Application
    Filed: January 27, 2022
    Publication date: September 22, 2022
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Juraj VAVRO
  • Patent number: 10249752
    Abstract: In one embodiment, the semiconductor devices relate to using one or more super-junction trenches for termination.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: April 2, 2019
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Zia Hossain, Juraj Vavro, Peter Moens
  • Patent number: 10134886
    Abstract: In one embodiment, an IGBT is formed to include a region of semiconductor material. Insulated gate structures are disposed in region of semiconductor material extending from a first major surface. An n-type field stop region extends from a second major surface into the region of semiconductor material. A p+ type polycrystalline semiconductor layer is disposed adjacent to the field stop region and provides an emitter region for the IGBT. An embodiment may include a portion of the p+ type polycrystalline semiconductor being doped n-type.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: November 20, 2018
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Marian Kuruc, Juraj Vavro
  • Publication number: 20180012995
    Abstract: In one embodiment, the semiconductor devices relate to using one or more super-junction trenches for termination.
    Type: Application
    Filed: September 5, 2017
    Publication date: January 11, 2018
    Applicant: Semiconductor Components Industries, LLC
    Inventors: Zia Hossain, Juraj Vavro, Peter Moens
  • Publication number: 20170323958
    Abstract: In one embodiment, an IGBT is formed to include a region of semiconductor material. Insulated gate structures are disposed in region of semiconductor material extending from a first major surface. An n-type field stop region extends from a second major surface into the region of semiconductor material. A p+ type polycrystalline semiconductor layer is disposed adjacent to the field stop region and provides an emitter region for the IGBT. An embodiment may include a portion of the p+ type polycrystalline semiconductor being doped n-type.
    Type: Application
    Filed: July 24, 2017
    Publication date: November 9, 2017
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Marian KURUC, Juraj VAVRO
  • Publication number: 20170271489
    Abstract: In one embodiment, an IGBT is formed to include a region of semiconductor material. Insulated gate structures are disposed in region of semiconductor material extending from a first major surface. An n-type field stop region extends from a second major surface into the region of semiconductor material. A p+ type polycrystalline semiconductor layer is disposed adjacent to the field stop region and provides an emitter region for the IGBT. An embodiment may include a portion of the p+ type polycrystalline semiconductor being doped n-type.
    Type: Application
    Filed: June 7, 2016
    Publication date: September 21, 2017
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Marian KURUC, Juraj VAVRO
  • Patent number: 9768285
    Abstract: In one embodiment, an IGBT is formed to include a region of semiconductor material. Insulated gate structures are disposed in region of semiconductor material extending from a first major surface. An n-type field stop region extends from a second major surface into the region of semiconductor material. A p+ type polycrystalline semiconductor layer is disposed adjacent to the field stop region and provides an emitter region for the IGBT. An embodiment may include a portion of the p+ type polycrystalline semiconductor being doped n-type.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: September 19, 2017
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Marian Kuruc, Juraj Vavro
  • Patent number: 9768295
    Abstract: In one embodiment, the semiconductor devices relate to using one or more super-junction trenches for termination.
    Type: Grant
    Filed: July 27, 2015
    Date of Patent: September 19, 2017
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Zia Hossain, Juraj Vavro, Peter Moens
  • Patent number: 9385202
    Abstract: In one embodiment, a semiconductor device includes an isolated trench-electrode structure. The semiconductor device is formed using a modified photolithographic process to produce alternating regions of thick and thin dielectric layers that separate the trench electrode from regions of the semiconductor device. The thin dielectric layers can be configured to control the formation channel regions, and the thick dielectric layers can be configured to reduce switching losses.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: July 5, 2016
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Marian Kuruc, Juraj Vavro
  • Publication number: 20150340434
    Abstract: In one embodiment, the semiconductor devices relate to using one or more super-junction trenches for termination.
    Type: Application
    Filed: July 27, 2015
    Publication date: November 26, 2015
    Applicant: Semiconductor Components Industries, LLC
    Inventors: Zia Hossain, Juraj Vavro, Peter Moens
  • Patent number: 9112026
    Abstract: In one embodiment, the semiconductor devices relate to using one or more super junction trenches for termination.
    Type: Grant
    Filed: October 17, 2012
    Date of Patent: August 18, 2015
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Zia Hossain, Juraj Vavro, Peter Moens
  • Publication number: 20150102403
    Abstract: In one embodiment, a semiconductor device includes an isolated trench-electrode structure. The semiconductor device is formed using a modified photolithographic process to produce alternating regions of thick and thin dielectric layers that separate the trench electrode from regions of the semiconductor device. The thin dielectric layers can be configured to control the formation channel regions, and the thick dielectric layers can be configured to reduce switching losses.
    Type: Application
    Filed: December 19, 2014
    Publication date: April 16, 2015
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Marian Kuruc, Juraj Vavro
  • Patent number: 8946002
    Abstract: In one embodiment, a semiconductor device includes an isolated trench-electrode structure. The semiconductor device is formed using a modified photolithographic process to produce alternating regions of thick and thin dielectric layers that separate the trench electrode from regions of the semiconductor device. The thin dielectric layers can be configured to control the formation channel regions, and the thick dielectric layers can be configured to reduce switching losses.
    Type: Grant
    Filed: July 24, 2012
    Date of Patent: February 3, 2015
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Marian Kuruc, Juraj Vavro
  • Publication number: 20140103421
    Abstract: In one embodiment, the semiconductor devices relate to using one or more super junction trenches for termination.
    Type: Application
    Filed: October 17, 2012
    Publication date: April 17, 2014
    Inventors: Zia Hossain, Juraj Vavro, Peter Moens