Patents by Inventor Jyh-Ming Jong

Jyh-Ming Jong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6504486
    Abstract: A process tracking reference voltage generator has been developed for an input/output system. The voltage generator includes a driver component that transmits an output signal to a receiver component. The receiver component generates a reference voltage in relation to the output signal as it varies with changing system operating conditions.
    Type: Grant
    Filed: November 6, 2000
    Date of Patent: January 7, 2003
    Assignee: Sun Microsystems, Inc.
    Inventors: Jyh-Ming Jong, Derek Tsai, Leo Yuan
  • Publication number: 20020186056
    Abstract: A method and circuitry for pre-emphasizing transmitted logic signals. The method and circuitry may be applied to single-ended center-taped terminated I/O lines. In one embodiment, a driver circuit may be configured for monitoring the logic values (i.e. logic 0, logic 1, or logic low, logic high) of signals transmitted by the driver circuit. The driver circuit may compare the logic value of a next logic signal to be transmitted with a first previously transmitted signal and a second previously transmitted signal. Pre-emphasis of the next logic signal may occur based on the logic value of the next logic signal to be transmitted as well as the logic values of the first and second logic signals. If the first and second logic signals have the same logic value, and the next logic signal has a different value, the next logic value may be pre-emphasized.
    Type: Application
    Filed: June 11, 2001
    Publication date: December 12, 2002
    Inventors: Jyh-Ming Jong, Prabhansu Chakrabarti, Leo Yuan
  • Publication number: 20020154718
    Abstract: A method and apparatus for operating a source synchronous receiver. In one embodiment, a source synchronous receiver may include a clock receiver comprising a clock detector and a clock signal buffer. The clock detector may be configured to detect a first clock signal and assert a clock detect signal responsive to detecting the first clock signal. The clock buffer may receive the first clock signal and produce a second clock signal, which may be driven to a digital locked loop (DLL) circuit, where the second clock signal is regenerated and driven to a data buffer of the source synchronous receiver. The clock detect signal may be received by a clock verification circuit. The clock verification circuit may be configured to initiate a reset of the source synchronous receiver upon a failure to receive the clock detect signal.
    Type: Application
    Filed: April 24, 2001
    Publication date: October 24, 2002
    Inventors: Wai Fong, Jyh-Ming Jong, Leo Yuan, Brian Smith, Prabhansu Chakrabarti
  • Publication number: 20020078392
    Abstract: One embodiment of the present invention provides a system for detecting a valid clock signal at a clock receiver. The system operates by receiving a clock signal at the clock receiver, and directing the clock signal into a control input of a voltage-controlled variable resistor. Next, the system uses the voltage-controlled variable resistor to control a first current. A current mirror is then employed to create a second current from the first current. This second current passes through a resistor to produce a control voltage, which is amplified to produce a validity signal indicating whether or not the clock signal is valid. In one embodiment of the present invention, the system additionally uses at least one capacitor to filter out periodic fluctuations in the validity signal.
    Type: Application
    Filed: December 18, 2000
    Publication date: June 20, 2002
    Inventors: Jyh-Ming Jong, Chung-Hsiao Wu, Prabhansu Chakrabarti, Leo Yuan
  • Patent number: 6404839
    Abstract: A clock divider circuit having a fifty per cent duty cycle and multiple integer ratios for dividing an input clock signal. In one embodiment, a clock divider circuit may include a chain of serially-coupled flip-flops. The chain may include at least a first and a second flip-flop, both of which may be triggered by a first edge of an input clock signal. A third flip-flop, coupled to (but not part of) the chain may be configured to be triggered by a second edge of the input clock signal. The third flip-flop may be coupled to an output circuit. In addition to receiving the output signal from the third flip-flop, the output circuit may also receive signals from the chain of serially-coupled flip-flops. The output circuit may drive a second clock signal, which may be produced by dividing the first clock signal based upon the signals it receives. The first clock signal may be divided by an even or an odd integer ratio, or may be divided by an integer ratio (e.g. 2.
    Type: Grant
    Filed: February 28, 2001
    Date of Patent: June 11, 2002
    Assignee: Sun Microsystems, Inc.
    Inventors: Wai Fong, Jyh-Ming Jong