Patents by Inventor Jyun-Siang Peng
Jyun-Siang Peng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230352442Abstract: A method includes encapsulating a device in an encapsulating material, planarizing the encapsulating material and the device, and forming a conductive feature over the encapsulating material and the device. The formation of the conductive feature includes depositing a first conductive material to from a first seed layer, depositing a second conductive material different from the first conductive material over the first seed layer to form a second seed layer, plating a metal region over the second seed layer, performing a first etching on the second seed layer, performing a second etching on the first seed layer, and after the first seed layer is etched, performing a third etching on the second seed layer and the metal region.Type: ApplicationFiled: July 10, 2023Publication date: November 2, 2023Inventors: Hui-Jung Tsai, Yun Chen Hsieh, Jyun-Siang Peng, Tai Min Chang, Yi-Yang Lei, Hung-Jui Kuo, Chen-Hua Yu
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Patent number: 11756879Abstract: A semiconductor device includes a die, a plurality of dielectric layers over the die, a via and at least one ring. The dielectric layers include a plurality of first surfaces facing the die. The via penetrates through the plurality of dielectric layers and includes at least one second surface facing the die. The ring surrounds the via and is disposed in at least one of the plurality of dielectric layers. The ring includes a third surface facing the die, wherein the third surface of the at least one ring is inserted between the at least one second surface of the via and the first surface of the at least one of the plurality of dielectric layers.Type: GrantFiled: August 6, 2021Date of Patent: September 12, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Keng-Han Lin, Jyun-Siang Peng
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Patent number: 11742317Abstract: A method includes encapsulating a device in an encapsulating material, planarizing the encapsulating material and the device, and forming a conductive feature over the encapsulating material and the device. The formation of the conductive feature includes depositing a first conductive material to from a first seed layer, depositing a second conductive material different from the first conductive material over the first seed layer to form a second seed layer, plating a metal region over the second seed layer, performing a first etching on the second seed layer, performing a second etching on the first seed layer, and after the first seed layer is etched, performing a third etching on the second seed layer and the metal region.Type: GrantFiled: October 17, 2019Date of Patent: August 29, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hui-Jung Tsai, Yun Chen Hsieh, Jyun-Siang Peng, Tai-Min Chang, Yi-Yang Lei, Hung-Jui Kuo, Chen-Hua Yu
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Publication number: 20230260898Abstract: A package structure includes at least one semiconductor die, an insulating encapsulant and a redistribution structure. The at least one semiconductor die has a plurality of conductive posts, wherein a top surface of the plurality of conductive posts has a first roughness. The insulating encapsulant is encapsulating the at least one semiconductor die. The redistribution structure is disposed on the insulating encapsulant in a build-up direction and is electrically connected to the at least one semiconductor die. The redistribution structure includes a plurality of conductive via portions and a plurality of conductive body portions embedded in dielectric layers, wherein a top surface of the plurality of conductive body portions has a second roughness, and the second roughness is greater than the first roughness.Type: ApplicationFiled: April 24, 2023Publication date: August 17, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Jyun-Siang Peng
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Patent number: 11670582Abstract: A package structure includes at least one semiconductor die, an insulating encapsulant and a redistribution structure. The at least one semiconductor die has a plurality of conductive posts, wherein a top surface of the plurality of conductive posts has a first roughness. The insulating encapsulant is encapsulating the at least one semiconductor die. The redistribution structure is disposed on the insulating encapsulant in a build-up direction and is electrically connected to the at least one semiconductor die. The redistribution structure includes a plurality of conductive via portions and a plurality of conductive body portions embedded in dielectric layers, wherein a top surface of the plurality of conductive body portions has a second roughness, and the second roughness is greater than the first roughness.Type: GrantFiled: February 14, 2022Date of Patent: June 6, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Jyun-Siang Peng
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Publication number: 20230111006Abstract: A method of fabricating an integrated fan-out package is provided. The method includes the following steps. An integrated circuit component is provided on a substrate. An insulating encapsulation is formed on the substrate to encapsulate sidewalls of the integrated circuit component. A redistribution circuit structure is formed along a build-up direction on the integrated circuit component and the insulating encapsulation. The formation of the redistribution circuit structure includes the following steps. A dielectric layer and a plurality of conductive vias embedded in the dielectric layer are formed, wherein a lateral dimension of each of the conductive vias decreases along the build-up direction. A plurality of conductive wirings is formed on the plurality of conductive vias and the dielectric layer. An integrated fan-out package of the same is also provided.Type: ApplicationFiled: December 12, 2022Publication date: April 13, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hui-Jung Tsai, Hung-Jui Kuo, Jyun-Siang Peng
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Patent number: 11587902Abstract: A method includes encapsulating a device in an encapsulating material, planarizing the encapsulating material and the device, and forming a conductive feature over the encapsulating material and the device. The formation of the conductive feature includes depositing a first conductive material to from a first seed layer, depositing a second conductive material different from the first conductive material over the first seed layer to form a second seed layer, plating a metal region over the second seed layer, performing a first etching on the second seed layer, performing a second etching on the first seed layer, and after the first seed layer is etched, performing a third etching on the second seed layer and the metal region.Type: GrantFiled: September 19, 2019Date of Patent: February 21, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hui-Jung Tsai, Yun Chen Hsieh, Jyun-Siang Peng, Tai-Min Chang, Yi-Yang Lei, Hung-Jui Kuo, Chen-Hua Yu
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Patent number: 11557561Abstract: A method of fabricating an integrated fan-out package is provided. The method includes the following steps. An integrated circuit component is provided on a substrate. An insulating encapsulation is formed on the substrate to encapsulate sidewalls of the integrated circuit component. A redistribution circuit structure is formed along a build-up direction on the integrated circuit component and the insulating encapsulation. The formation of the redistribution circuit structure includes the following steps. A dielectric layer and a plurality of conductive vias embedded in the dielectric layer are formed, wherein a lateral dimension of each of the conductive vias decreases along the build-up direction. A plurality of conductive wirings is formed on the plurality of conductive vias and the dielectric layer. An integrated fan-out package of the same is also provided.Type: GrantFiled: November 29, 2020Date of Patent: January 17, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hui-Jung Tsai, Hung-Jui Kuo, Jyun-Siang Peng
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Publication number: 20220359359Abstract: A conductive structure, a semiconductor package and methods of forming the same are disclosed. A conductive structure includes a metal feature, an insulating layer and a nitridized metal layer. The metal feature is disposed over a substrate and includes a lower metal pattern and an upper metal pattern over the lower metal pattern. The insulating layer surrounds the metal feature. The nitridized metal layer is disposed between the lower metal pattern and the upper metal pattern.Type: ApplicationFiled: July 25, 2022Publication date: November 10, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Jyun-Siang Peng, Chia-Wei Wang
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Publication number: 20220173033Abstract: A package structure includes at least one semiconductor die, an insulating encapsulant and a redistribution structure. The at least one semiconductor die has a plurality of conductive posts, wherein a top surface of the plurality of conductive posts has a first roughness. The insulating encapsulant is encapsulating the at least one semiconductor die. The redistribution structure is disposed on the insulating encapsulant in a build-up direction and is electrically connected to the at least one semiconductor die. The redistribution structure includes a plurality of conductive via portions and a plurality of conductive body portions embedded in dielectric layers, wherein a top surface of the plurality of conductive body portions has a second roughness, and the second roughness is greater than the first roughness.Type: ApplicationFiled: February 14, 2022Publication date: June 2, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Jyun-Siang Peng
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Patent number: 11251121Abstract: A package structure includes at least one semiconductor die, an insulating encapsulant and a redistribution structure. The at least one semiconductor die has a plurality of conductive posts, wherein a top surface of the plurality of conductive posts has a first roughness. The insulating encapsulant is encapsulating the at least one semiconductor die. The redistribution structure is disposed on the insulating encapsulant in a build-up direction and is electrically connected to the at least one semiconductor die. The redistribution structure includes a plurality of conductive via portions and a plurality of conductive body portions embedded in dielectric layers, wherein a top surface of the plurality of conductive body portions has a second roughness, and the second roughness is greater than the first roughness.Type: GrantFiled: July 14, 2020Date of Patent: February 15, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Jyun-Siang Peng
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Publication number: 20210366826Abstract: A semiconductor device includes a die, a plurality of dielectric layers over the die, a via and at least one ring. The dielectric layers include a plurality of first surfaces facing the die. The via penetrates through the plurality of dielectric layers and includes at least one second surface facing the die. The ring surrounds the via and is disposed in at least one of the plurality of dielectric layers. The ring includes a third surface facing the die, wherein the third surface of the at least one ring is inserted between the at least one second surface of the via and the first surface of the at least one of the plurality of dielectric layers.Type: ApplicationFiled: August 6, 2021Publication date: November 25, 2021Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Keng-Han Lin, Jyun-Siang Peng
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Patent number: 11127701Abstract: The present disclosure provides a method of manufacturing a semiconductor package. Semiconductor dies having conductive pillars are provided and are encapsulated with an insulating encapsulant. A redistribution circuit structure is formed on the insulating encapsulant and the semiconductor dies, and the redistribution circuit structure is electrically connected to the semiconductor dies. A photosensitive mask pattern having a plurality of openings is formed. A plurality of conductive vias is formed within the openings of the photosensitive mask pattern. A dielectric layer is then formed, and the conductive vias are embedded in the dielectric layer.Type: GrantFiled: June 17, 2019Date of Patent: September 21, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Jyun-Siang Peng
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Patent number: 11088068Abstract: Semiconductor packages and methods of forming the same are disclosed. The semiconductor package includes a package, a device and a screw. The package includes a plurality of dies, an encapsulant encapsulating the plurality of dies, and a redistribution structure over the plurality of dies and the encapsulant. The device is disposed over the package, wherein the dies and the encapsulant are disposed between the device and the redistribution structure. The screw penetrates through the package and the device.Type: GrantFiled: April 29, 2019Date of Patent: August 10, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Keng-Han Lin, Jyun-Siang Peng
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Publication number: 20210118786Abstract: A conductive structure, a semiconductor package and methods of forming the same are disclosed. A conductive structure includes a metal feature, an insulating layer and a nitridized metal layer. The metal feature is disposed over a substrate and includes a lower metal pattern and an upper metal pattern over the lower metal pattern. The insulating layer surrounds the metal feature. The nitridized metal layer is disposed between the lower metal pattern and the upper metal pattern.Type: ApplicationFiled: October 16, 2019Publication date: April 22, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Jyun-Siang Peng, Chia-Wei Wang
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Publication number: 20210090995Abstract: A package structure includes at least one semiconductor die, an insulating encapsulant and a redistribution structure. The at least one semiconductor die has a plurality of conductive posts, wherein a top surface of the plurality of conductive posts has a first roughness. The insulating encapsulant is encapsulating the at least one semiconductor die. The redistribution structure is disposed on the insulating encapsulant in a build-up direction and is electrically connected to the at least one semiconductor die. The redistribution structure includes a plurality of conductive via portions and a plurality of conductive body portions embedded in dielectric layers, wherein a top surface of the plurality of conductive body portions has a second roughness, and the second roughness is greater than the first roughness.Type: ApplicationFiled: July 14, 2020Publication date: March 25, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Jyun-Siang Peng
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Publication number: 20210082858Abstract: A method of fabricating an integrated fan-out package is provided. The method includes the following steps. An integrated circuit component is provided on a substrate. An insulating encapsulation is formed on the substrate to encapsulate sidewalls of the integrated circuit component. A redistribution circuit structure is formed along a build-up direction on the integrated circuit component and the insulating encapsulation. The formation of the redistribution circuit structure includes the following steps. A dielectric layer and a plurality of conductive vias embedded in the dielectric layer are formed, wherein a lateral dimension of each of the conductive vias decreases along the build-up direction. A plurality of conductive wirings is formed on the plurality of conductive vias and the dielectric layer. An integrated fan-out package of the same is also provided.Type: ApplicationFiled: November 29, 2020Publication date: March 18, 2021Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hui-Jung Tsai, Hung-Jui Kuo, Jyun-Siang Peng
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Patent number: 10879161Abstract: Conductive structures, semiconductor packages and methods of forming the same are disclosed. A semiconductor package includes at least one die and a redistribution layer. The redistribution layer is disposed over and electrically to the at least one die and includes a seed layer structure and a metal feature over the seed layer structure. In some embodiments, an edge of the seed layer structure is protruded from an edge of the metal feature and has a surface roughness Rz greater than 10 nm.Type: GrantFiled: June 5, 2019Date of Patent: December 29, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Jyun-Siang Peng, Chien-Tang Peng
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Patent number: 10879199Abstract: The present disclosure provides a method of fabricating an integrated fan-out package including the following steps. A semiconductor die is laterally encapsulated by an insulating encapsulant. A redistribution circuit structure is formed on the insulating encapsulant and the semiconductor die, and the redistribution circuit structure is electrically connected to the semiconductor die. A forming method of the redistribution circuit structure includes the following steps. A conductive wiring is formed over the insulating encapsulant and the semiconductor die. A dielectric material is formed on the insulating encapsulant and the semiconductor die to cover the conductive wiring. A sacrificial layer is formed on the dielectric material, wherein a first top surface of the sacrificial layer is flatter than a second top surface of the dielectric material.Type: GrantFiled: August 7, 2019Date of Patent: December 29, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Jyun-Siang Peng
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Publication number: 20200395319Abstract: The present disclosure provides a method of manufacturing a semiconductor package. Semiconductor dies having conductive pillars are provided and are encapsulated with an insulating encapsulant. A redistribution circuit structure is formed on the insulating encapsulant and the semiconductor dies, and the redistribution circuit structure is electrically connected to the semiconductor dies. A photosensitive mask pattern having a plurality of openings is formed. A plurality of conductive vias is formed within the openings of the photosensitive mask pattern. A dielectric layer is then formed, and the conductive vias are embedded in the dielectric layer.Type: ApplicationFiled: June 17, 2019Publication date: December 17, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Jyun-Siang Peng