Patents by Inventor K. S. Sankara Reddy

K. S. Sankara Reddy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8004345
    Abstract: A system and method for minimizing non-linearity errors induced in output drive voltage of a transmitter circuit due to on-chip process, voltage, and temperature (PVT) variations. The system including an oscillator for converting an input reference bias voltage into a clock output signal, where the input reference bias voltage varies in response to PVT variations. Also included is a counter for counting the clock output signal and generating a count value corresponding to the clock output of the oscillator. A comparison module operatively coupled to the counter compares the count value with a pre-simulated count value to generate an error signal. Based on the error signal generated by the comparison module, a correction logic adjusts an output drive signal of the transmitter circuit making it immune to PVT variations.
    Type: Grant
    Filed: June 25, 2009
    Date of Patent: August 23, 2011
    Assignee: International Business Machines Corporation
    Inventors: Navin Kumar Ramamoorthy, Umesh K Shukla, K. S. Sankara Reddy
  • Publication number: 20100327950
    Abstract: A system and method for minimizing non-linearity errors induced in output drive voltage of a transmitter circuit due to on-chip process, voltage, and temperature (PVT) variations. The system including an oscillator for converting an input reference bias voltage into a clock output signal, where the input reference bias voltage varies in response to PVT variations. Also included is a counter for counting the clock output signal and generating a count value corresponding to the clock output of the oscillator. A comparison module operatively coupled to the counter compares the count value with a pre-simulated count value to generate an error signal. Based on the error signal generated by the comparison module, a correction logic adjusts an output drive signal of the transmitter circuit making it immune to PVT variations.
    Type: Application
    Filed: June 25, 2009
    Publication date: December 30, 2010
    Applicant: International Business Machines Corporation
    Inventors: Navin Kumar Ramamoorthy, Umesh K. Shukla, K.S. Sankara Reddy