Abstract: Techniques for reading a Multi-Bit Cell (MBC) can include sensing a state parameter value, such as source line voltage, and applying a successive one of N programming parameter values, such as successive programming currents, between instances of sensing the state parameter values. The N successive programming parameter values can be selected to program the state of a corresponding one of N cell elements of the MBC to a respective state parameter value. Successive ones of the sensed state parameter values can be compared to determine N state change results, which can be used to determine the read state of the MBC.

Abstract: An apparatus includes two or more magnetic tunnel junctions (MTJs), including a first MTJ having a first magnetic characteristic and a second MTJ having a second magnetic characteristic. The first magnetic characteristic is distinct from the second magnetic characteristic. The first magnetic characteristic is based on a first magnetic anisotropy and a first offset field on a first storage layer of the first MTJ. The second magnetic characteristic is based on a second magnetic anisotropy and a second offset field on a second storage layer of the second MTJ, The apparatus further includes a metallic separator coupling the first MTJ with the second MTJ, wherein the first MTJ and the second MTJ are arranged in series.

Abstract: A method of writing data into a memory device is disclosed. The method comprises utilizing a pipeline to process write operations of a first plurality of data words addressed to a memory bank and writing a second plurality of data words and associated memory addresses into an error buffer. The method also comprises monitoring a first counter value which tracks a number of write 1 errors and a second counter value which tracks a number of write 0 errors in the memory bank. Further, the method comprises determining if the first counter value and the second counter value have exceeded a predetermined threshold. Responsive to a determination that the first counter value has exceeded the predetermined threshold increasing a write 1 voltage of the memory bank, and, further, responsive to a determination that the second counter value has exceeded the predetermined threshold increasing a write 0 voltage of the memory bank.

Abstract: A method for forming three-dimensional magnetic memory arrays by forming crystalized silicon structures from amorphous structures in the magnetic memory array, wherein the temperature needed to crystalize the amorphous silicon is lower than the temperature budget of the memory element so as to avoid damage to the memory element. An amorphous silicon is deposited, followed by a layer of Ti or Co. An annealing process is then performed which causes the Ti or Co to form TiSi2 or CoSi2 and also causes the underlying amorphous silicon to crystallize.

Abstract: Techniques for reading a Multi-Bit Cell (MBC) can include sensing a state parameter value, such as source line voltage, and applying a successive one of N programming parameter values, such as successive programming currents, between instances of sensing the state parameter values. The N successive programming parameter values can be selected to switch the state of a corresponding one of N cell elements of the MBC. Successive ones of the sensed state parameter values can be compared to determine N state change results, which can be used to determine the read state of the MBC.

Abstract: Techniques for reading a Multi-Bit Cell (MBC) can include sensing a state parameter value, such as source line voltage, and applying a successive one of N programming parameter values, such as successive programming currents, between instances of sensing the state parameter values. The N successive programming parameter values can be selected to program the state of a corresponding one of N cell elements of the MBC to a respective state parameter value. Successive ones of the sensed state parameter values can be compared to determine N state change results, which can be used to determine the read state of the MBC.

Abstract: A method for crystalized silicon structures from amorphous structures in a magnetic memory array, wherein the temperature needed to crystalize the amorphous silicon is lower than the temperature budget of the memory element so as to avoid damage to the memory element. An amorphous silicon is deposited, followed by a layer of Ti or Co. An annealing process is then performed which causes the Ti or Co to form TiSi2 or CoSi2 and also causes the underlying amorphous silicon to crystallize.

Abstract: Techniques for reading a Multi-Bit Cell (MBC) can include sensing a state parameter value, such as source line voltage, and applying a successive one of N programming parameter values, such as successive programming currents, between instances of sensing the state parameter values. The N successive programming parameter values can be selected to switch the state of a corresponding one of N cell elements of the MBC. Successive ones of the sensed state parameter values can be compared to determine N state change results, which can be used to determine the read state of the MBC.

Abstract: A magnetic device, according to one approach, includes: a plurality of perpendicular magnetic tunnel junction (p-MTJ) cells, each p-MTJ cell having a transistor and a magnetic tunnel junction (MTJ) sensor. Moreover, each of the transistors includes a drain terminal, a source terminal, and a gate terminal. The magnetic device also includes: a first common word line coupled to the gate terminal of each transistor in a first subset of the plurality of p-MTJ cells, a first common bit line coupled to a first end of each MTJ sensor in a second subset of the plurality of p-MTJ cells, and a first common source line coupled to the drain terminal of each transistor in the first subset. A second end of each of the MTJ sensors in the second subset is coupled to the source terminal of each respective transistor in the second subset.

Abstract: A memory cell apparatus is provided. The apparatus comprises two or more magnetic tunnel junctions (MTJs), including a first MTJ having a first magnetic characteristic and a first electrical characteristic and a second MTJ having a second magnetic characteristic and a second electrical characteristic. The first magnetic characteristic is distinct from the second magnetic characteristic. The apparatus further comprises a transistor having three terminals, where the first MTJ is coupled to a first terminal of the three terminals and a metallic separator coupling the first MTJ with the second MTJ. The first MTJ and the second MTJ are arranged in series.

Abstract: Methods and structures useful for magnetoresistive random-access memory (MRAM) are disclosed. The MRAM device has a magnetic tunnel junction stack having a significantly improved performance of the free layer in the magnetic tunnel junction structure. The MRAM device utilizes an in-plane polarization magnetic layer and a perpendicular MTJ in conjugation with a alternating current precharge and a programming current pulse that comprises an alternating perturbation frequency and a direct current.

Abstract: A magnetic storage device is provided. The magnetic storage device comprises a magnetic memory cell, which includes two or more magnetic tunnel junctions (MTJs), including a first MTJ having a first magnetic characteristic and a first electrical characteristic and a second MTJ has a second magnetic characteristic and a second electrical characteristic, wherein the first magnetic characteristic is distinct from the second magnetic characteristic. The magnetic memory cell further comprises a bottom electrode and a top electrode, wherein the two or more MTJs are arranged between the top and bottom electrode in parallel with respect to each other. The magnetic storage device further comprises readout circuitry coupled to the bottom electrode or the top electrode of the magnetic memory cell and write circuitry coupled to the bottom electrode or the top electrode of the magnetic memory cell.

Abstract: The various implementations described herein include methods, devices, and systems for operating magnetic memory devices. In one aspect, a magnetic memory device includes: (1) a core; (2) a plurality of layers that surround the core in succession; (3) a first input terminal coupled to the core and configured to receive a first current, where: (a) the first current flows radially from the core through the plurality of layers; and (b) the radial flow of the first current imparts a torque on, at least, a magnetization of an inner layer of the plurality of layers; and (4) a second input terminal coupled to the core and configured to receive a second current, where: (i) the second current imparts a Spin Hall Effect (SHE) around a perimeter of the core; and (ii) the SHE contributes to the torque imparted on the magnetization of the inner layer by the first current.

Abstract: A magnetic device, according to one approach, includes: a plurality of perpendicular magnetic tunnel junction (p-MTJ) cells, each p-MTJ cell having a transistor and a magnetic tunnel junction (MTJ) sensor. Moreover, each of the transistors includes a drain terminal, a source terminal, and a gate terminal. The magnetic device also includes: a first common word line coupled to the gate terminal of each transistor in a first subset of the plurality of p-MTJ cells, a first common bit line coupled to a first end of each MTJ sensor in a second subset of the plurality of p-MTJ cells, and a first common source line coupled to the drain terminal of each transistor in the first subset. A second end of each of the MTJ sensors in the second subset is coupled to the source terminal of each respective transistor in the second subset.

Abstract: A magnetic storage device is provided. The magnetic storage device comprises a magnetic memory cell, which includes two or more magnetic tunnel junctions (MTJs), including a first MTJ having a first magnetic characteristic and a first electrical characteristic and a second MTJ has a second magnetic characteristic and a second electrical characteristic, wherein the first magnetic characteristic is distinct from the second magnetic characteristic. The magnetic memory cell further comprises a bottom electrode and a top electrode, wherein the two or more MTJs are arranged between the top and bottom electrode in parallel with respect to each other. The magnetic storage device further comprises readout circuitry coupled to the bottom electrode or the top electrode of the magnetic memory cell and write circuitry coupled to the bottom electrode or the top electrode of the magnetic memory cell.

Abstract: A memory cell apparatus is provided. The apparatus comprises two or more magnetic tunnel junctions (MTJs), including a first MTJ having a first magnetic characteristic and a first electrical characteristic and a second MTJ having a second magnetic characteristic and a second electrical characteristic. The first magnetic characteristic is distinct from the second magnetic characteristic. The apparatus further comprises a transistor having three terminals, where the first MTJ is coupled to a first terminal of the three terminals and a metallic separator coupling the first MTJ with the second MTJ. The first MTJ and the second MTJ are arranged in series.

Abstract: Methods and structures useful for magnetoresistive random-access memory (MRAM) are disclosed. The MRAM device has a magnetic tunnel junction stack having a significantly improved performance of the free layer in the magnetic tunnel junction structure. The MRAM device utilizes an in-plane polarization magnetic layer and a perpendicular MTJ in conjugation with a alternating current precharge and a programming current pulse that comprises an alternating perturbation frequency and a direct current.

Abstract: A method for selectively writing to STT-MRAM using an AC current is provided. The method is performed in a memory device including two or more multilevel magnetic tunnel junctions (MTJs) arranged in series with respect to a single terminal of a transistor, where the two or more multilevel MTJs include a first MTJ having a first magnetic characteristic and first electrical characteristic and a second MTJ having a second magnetic characteristic that is distinct from the first magnetic characteristic and a second electrical characteristic. The method includes writing to an MTJ. The writing includes applying a DC current to the two or more MTJs and applying an AC current to the two or more MTJs, where the AC current is adjusted to a frequency that is tuned to a write assist frequency corresponding to the respective MTJ.

Abstract: The various implementations described herein include methods, devices, and systems for operating magnetic memory devices. In one aspect, a magnetic memory device includes: (1) a core; (2) a plurality of layers that surround the core in succession; (3) a first input terminal coupled to the core and configured to receive a first current, where: (a) the first current flows radially from the core through the plurality of layers; and (b) the radial flow of the first current imparts a torque on, at least, a magnetization of an inner layer of the plurality of layers; and (4) a second input terminal coupled to the core and configured to receive a second current, where: (i) the second current imparts a Spin Hall Effect (SHE) around a perimeter of the core; and (ii) the SHE contributes to the torque imparted on the magnetization of the inner layer by the first current.

Abstract: Methods and structures useful for magnetoresistive random-access memory (MRAM) are disclosed. The MRAM device has a magnetic tunnel junction stack having a significantly improved performance of the free layer in the magnetic tunnel junction structure. The MRAM device utilizes a STNO, an in-plane polarization magnetic layer, and a perpendicular MTJ.