Patents by Inventor Kai-Jyun Huang

Kai-Jyun Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220393693
    Abstract: An analog-to-digital converter includes a switch circuit, a first capacitor array, a second capacitor array and a comparator. A method of operating the analog-to-digital converter includes switching a swap signal to a first level in a first sampling period for the switch circuit to couple the first capacitor array to a first input terminal of the comparator and a first signal source, and couple the second capacitor array to a second input terminal of the comparator and a second signal source, and switching the swap signal to a second level in a second sampling period for the switch circuit to couple the first capacitor array to the second input terminal of the comparator and the second signal source, and couple the second capacitor array to the first input terminal of the comparator and the first signal source.
    Type: Application
    Filed: December 14, 2021
    Publication date: December 8, 2022
    Applicant: Realtek Semiconductor Corp.
    Inventors: Kai-Yue Lin, Wei-Jyun Wang, Shih-Hsiung Huang, Kai-Yin Liu
  • Publication number: 20220393694
    Abstract: A method of operating an analog-to-digital converter includes in a first conversion period, a comparator generating a first comparison result, a first selection circuit switching a voltage output to a first capacitor of a set of larger capacitor of a first capacitor array, and a second selection circuit switching a voltage output to a second capacitor of a set of larger capacitor of a second capacitor array, and in a second conversion period after the first conversion period, the comparator generating a second comparison result different from the first comparison result, the first selection circuit switching back the voltage output to a first capacitor portion of the first capacitor of the set of larger capacitor of the first capacitor array, and the second selection circuit switching back the voltage output to a first capacitor portion of the second capacitor of the set of larger capacitor of the second capacitor array.
    Type: Application
    Filed: November 3, 2021
    Publication date: December 8, 2022
    Applicant: Realtek Semiconductor Corp.
    Inventors: Kai-Yue Lin, Wei-Jyun Wang, Shih-Hsiung Huang, Kai-Yin Liu
  • Patent number: 11489539
    Abstract: A method of operating an analog-to-digital converter includes in a first sampling stage, switching a swap signal to a first level for a first selection circuit to reset a first capacitor array according to a first voltage configuration and for a second selection circuit to reset a second capacitor array according to the first voltage configuration, and in a second sampling stage, switching the swap signal to a second level for the first selection circuit to reset the first capacitor array according to the second voltage configuration and for the second selection circuit to reset the second capacitor array according to the second voltage configuration. A control logic circuit is used to switch the swap signal between the first level and the second level in a uniform order in a plurality of sampling stages.
    Type: Grant
    Filed: September 13, 2021
    Date of Patent: November 1, 2022
    Assignee: Realtek Semiconductor Corp.
    Inventors: Kai-Yue Lin, Wei-Jyun Wang, Shih-Hsiung Huang, Kai-Yin Liu
  • Publication number: 20220337259
    Abstract: The present invention discloses an analog to digital conversion (ADC) apparatus having quick conversion mechanism. Each of ADC circuits receives a previous higher-bit conversion result to perform prediction to generate a current higher-bit conversion result, performs conversion on an input analog signal according to a sampling clock that has a frequency at least twice of the frequency of the input analog signal based on a successive-approximation mechanism to generate a current lower-bit conversion result, and combines the current higher-bits and current lower-bit conversion results to generate a current conversion result and output a remained signal amount as a residue. A noise-shaping circuit performs calculation based on the residue to generate a noise-shaping reference signal. Each of the ADC circuits combines the current conversion result and the noise-shaping reference signal to generate an output digital signal.
    Type: Application
    Filed: February 14, 2022
    Publication date: October 20, 2022
    Inventors: SHIH-HSIUNG HUANG, KAI-YUE LIN, WEI-JYUN WANG, SHENG-YEN SHIH
  • Patent number: 11476864
    Abstract: A control circuit of a pipeline analog-to-digital converter (ADC) is provided. The pipeline ADC includes a multiplying digital-to-analog converter (MDAC) which includes a capacitor. The control circuit includes six switches and two buffer circuits. The first and second switches are respectively coupled between one end of the capacitor and the first and second reference voltages. The output terminals of the first and second buffer circuits are respectively coupled to the first and second switches. The input terminal of the first buffer circuit is coupled to the third reference voltage through the third switch, or receives a control signal through the fifth switch. The input terminal of the second buffer circuit is coupled to the fourth reference voltage through the fourth switch, or receives the control signal through the sixth switch. The first and second reference voltages are different, and the first and second switches are not turned on simultaneously.
    Type: Grant
    Filed: August 24, 2021
    Date of Patent: October 18, 2022
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Pan Zhang, Kai-Yin Liu, Shih-Hsiung Huang, Wei-Jyun Wang
  • Publication number: 20220329253
    Abstract: A method of operating an analog-to-digital converter includes in a first sampling stage, switching a swap signal to a first level for a first selection circuit to reset a first capacitor array according to a first voltage configuration and for a second selection circuit to reset a second capacitor array according to the first voltage configuration, and in a second sampling stage, switching the swap signal to a second level for the first selection circuit to reset the first capacitor array according to the second voltage configuration and for the second selection circuit to reset the second capacitor array according to the second voltage configuration. A control logic circuit is used to switch the swap signal between the first level and the second level in a uniform order in a plurality of sampling stages.
    Type: Application
    Filed: September 13, 2021
    Publication date: October 13, 2022
    Applicant: Realtek Semiconductor Corp.
    Inventors: Kai-Yue Lin, Wei-Jyun Wang, Shih-Hsiung Huang, Kai-Yin Liu
  • Publication number: 20220310781
    Abstract: A method of manufacturing a capacitor structure of memory, including forming a patterned photoresist layer on a hard mask layer and spacers on sidewalls of the patterned photoresist layer, perform a first etch process to remove uncovered hard mask layer so as to form first patterned hard mask layer and expose first portion of the dielectric layer, lowering a surface of the first portion of dielectric layer, perform a second etch process to remove uncovered first patterned hard mask layer so as to form second patterned hard mask layer and expose second portion of the dielectric layer, and performing a hole etching process to form first holes and second holes respectively in the first portion and the second portion of dielectric layer, wherein sidewalls of the first holes and second holes have wavelike cross-sections, and the wavelike cross-sections of first holes and second holes are shifted vertically by a distance.
    Type: Application
    Filed: June 13, 2022
    Publication date: September 29, 2022
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventor: Kai-Jyun Huang
  • Patent number: 11393897
    Abstract: A capacitor structure of memory is provided in the present invention, including structures of multiple cylindrical bottom electrode layers with bottoms contacting a substrate and extending vertically and upwardly from the substrate, the cylindrical shape of the bottom electrode layer has a sidewall with wavelike cross-section, and the wavelike cross-sections of adjacent bottom electrode layers are identical but shifted vertically by a distance, a capacitive dielectric layer on the bottom electrode layers, and a top electrode layer on the capacitive dielectric layer.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: July 19, 2022
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventor: Kai-Jyun Huang
  • Publication number: 20220149149
    Abstract: A capacitor structure of memory is provided in the present invention, including structures of multiple cylindrical bottom electrode layers with bottoms contacting a substrate and extending vertically and upwardly from the substrate, the cylindrical shape of the bottom electrode layer has a sidewall with wavelike cross-section, and the wavelike cross-sections of adjacent bottom electrode layers are identical but shifted vertically by a distance, a capacitive dielectric layer on the bottom electrode layers, and a top electrode layer on the capacitive dielectric layer.
    Type: Application
    Filed: March 15, 2021
    Publication date: May 12, 2022
    Inventor: Kai-Jyun Huang