Abstract: A high voltage semiconductor device includes a semiconductor substrate, first and second deep well regions, and first and second well regions disposed in the semiconductor substrate. The second deep well region is located above the first deep well region. The first well region is located above the first deep well region. The second well region is located above the second deep well region. A conductivity type of the second deep well region is complementary to that of the first deep well region. A conductivity type of the second well region is complementary to that of the first well region and the second deep well region. A length of the second deep well region is greater than or equal to that of the second well region and less than that of the first deep well region. The first well region is connected with the first deep well region.

Abstract: A semiconductor substrate is provided. A trench isolation region is formed in the semiconductor substrate. A resist pattern having an opening exposing the trench isolation region and partially exposing the semiconductor substrate is disposed adjacent to the trench isolation region. A first ion implantation process is performed to implant first dopants into the semiconductor substrate through the opening, thereby forming a well region in the semiconductor substrate. The trench isolation region is within the well region. A second ion implantation process is performed to implant second dopants into the semiconductor substrate through the opening, thereby forming an extended doped region contiguous with the well region. The resist pattern is then removed. After removing the resist pattern, a gate dielectric layer is formed on the semiconductor substrate. A gate is then formed on the gate dielectric layer. The gate overlaps with the extended doped region.

Abstract: A semiconductor substrate is provided. A trench isolation region is formed in the semiconductor substrate. A resist pattern having an opening exposing the trench isolation region and partially exposing the semiconductor substrate is disposed adjacent to the trench isolation region. A first ion implantation process is performed to implant first dopants into the semiconductor substrate through the opening, thereby forming a well region in the semiconductor substrate. The trench isolation region is within the well region. A second ion implantation process is performed to implant second dopants into the semiconductor substrate through the opening, thereby forming an extended doped region contiguous with the well region. The resist pattern is then removed. After removing the resist pattern, a gate dielectric layer is formed on the semiconductor substrate. A gate is then formed on the gate dielectric layer. The gate overlaps with the extended doped region.

Abstract: A method of energy management includes steps of: deciding system parameters; determining an object function; obtaining characteristics information and predetermined ranges respectively of the system parameters; calculating function values of the object function for various parameter value combinations of the system parameters within the predetermined ranges based on the characteristics information so as to establish a database; determining a smallest function value among those of the function values in the database that satisfy certain conditions; and determining an optimum power split ratio based on the parameter value combination corresponding to the smallest function value for energy management of the vehicle.

Abstract: A high voltage transistor structure includes a substrate. A metal gate is disposed on the substrate. At least one insulating material structure penetrates the metal gate. A metal compound layer is disposed between the metal gate and the substrate, between the insulating material structure and the substrate. The metal compound layer is a continuous structure. A gate dielectric layer is disposed under the metal compound layer and contacts the substrate.

Abstract: A high voltage transistor structure includes a substrate. A metal gate is disposed on the substrate. At least one insulating material structure penetrates the metal gate. A metal compound layer is disposed between the metal gate and the substrate, between the insulating material structure and the substrate. The metal compound layer is a continuous structure. Agate dielectric layer is disposed under the metal compound layer and contacts the substrate.

Abstract: A high electron mobility transistor (HEMT) includes a gallium nitride layer. An aluminum gallium nitride layer is disposed on the gallium nitride layer, wherein the aluminum gallium nitride layer comprises a tensile stress. A source electrode and a drain electrode are disposed on the aluminum gallium nitride layer. A gate electrode is disposed on the aluminum gallium nitride layer between the source electrode and the drain electrode. At least one silicon oxide layer is embedded in the aluminum gallium nitride layer, wherein the silicon oxide layer is formed by a flowable chemical vapor deposition, and the silicon oxide layer increases the tensile stress in the aluminum gallium nitride layer.

Abstract: A high voltage transistor structure includes a substrate. A metal gate is disposed on the substrate. At least one insulating material structure penetrates the metal gate. A metal compound layer is disposed between the metal gate and the substrate, between the insulating material structure and the substrate. The metal compound layer is a continuous structure. Agate dielectric layer is disposed under the metal compound layer and contacts the substrate.

Abstract: A method of fabricating a metal gate transistor includes providing a substrate. An interlayer dielectric layer covers the substrate. A dummy gate is embedded in the interlayer dielectric layer. A high-k dielectric layer is disposed between the dummy gate and the substrate. Later, the dummy gate is removed to form a trench, and the high-k dielectric layer is exposed through the trench. After the dummy gate is removed, an ion implantation process is performed to implant fluoride ions into the high-k dielectric layer. Finally, after the ion implantation process, a metal gate is formed to fill in the trench.

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a hard mask on the barrier layer; removing the hard mask to form a first recess for exposing the barrier layer; removing the hard mask adjacent to the first recess to form a second recess; and forming a p-type semiconductor layer in the first recess and the second recess.

Abstract: A method of fabricating a metal gate transistor includes providing a substrate. An interlayer dielectric layer covers the substrate. A dummy gate is embedded in the interlayer dielectric layer. A high-k dielectric layer is disposed between the dummy gate and the substrate. Later, the dummy gate is removed to form a trench, and the high-k dielectric layer is exposed through the trench. After the dummy gate is removed, an ion implantation process is performed to implant fluoride ions into the high-k dielectric layer. Finally, after the ion implantation process, a metal gate is formed to fill in the trench.

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a hard mask on the barrier layer; removing the hard mask to form a first recess for exposing the barrier layer; removing the hard mask adjacent to the first recess to form a second recess; and forming a p-type semiconductor layer in the first recess and the second recess.

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region; forming a first gate structure and a second gate structure on the first fin-shaped structure; using a patterned mask to remove the first gate structure and part of the first fin-shaped structure to form a first trench; and forming a first dielectric layer in the first trench to form a first single diffusion break (SDB) structure and around the second gate structure.

Abstract: A method of fabricating a metal gate transistor includes providing a substrate. An interlayer dielectric layer covers the substrate. A dummy gate is embedded in the interlayer dielectric layer. A high-k dielectric layer is disposed between the dummy gate and the substrate. Later, the dummy gate is removed to form a trench, and the high-k dielectric layer is exposed through the trench. After the dummy gate is removed, an ion implantation process is performed to implant fluoride ions into the high-k dielectric layer. Finally, after the ion implantation process, a metal gate is formed to fill in the trench.

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a hard mask on the barrier layer; removing the hard mask to form a first recess for exposing the barrier layer; removing the hard mask adjacent to the first recess to form a second recess; and forming a p-type semiconductor layer in the first recess and the second recess.

Abstract: A semiconductor structure includes at least one stacked fin structure, a gate and a source/drain. At least one stacked fin structure is located on a substrate, wherein the stacked fin structure includes a first fin layer and a second fin layer, and a fin dielectric layer is sandwiched by the first fin layer and the second fin layer. The gate is disposed over the stacked fin structure. The source/drain is disposed directly on the substrate and directly on sidewalls of the whole stacked fin structure. The present invention provides a semiconductor process formed said semiconductor structure.

Abstract: A high electron mobility transistor (HEMT) includes a gallium nitride layer. An aluminum gallium nitride layer is disposed on the gallium nitride layer, wherein the aluminum gallium nitride layer comprises a tensile stress. A source electrode and a drain electrode are disposed on the aluminum gallium nitride layer. A gate electrode is disposed on the aluminum gallium nitride layer between the source electrode and the drain electrode. At least one silicon oxide layer is embedded in the aluminum gallium nitride layer, wherein the silicon oxide layer is formed by a flowable chemical vapor deposition, and the silicon oxide layer increases the tensile stress in the aluminum gallium nitride layer.

Abstract: A method of energy management includes steps of: deciding system parameters; determining an object function; obtaining characteristics information and predetermined ranges respectively of the system parameters; calculating function values of the object function for various parameter value combinations of the system parameters within the predetermined ranges based on the characteristics information so as to establish a database; determining a smallest function value among those of the function values in the database that satisfy certain conditions; and determining an optimum power split ratio based on the parameter value combination corresponding to the smallest function value for energy management of the vehicle.

Abstract: A semiconductor structure includes at least one stacked fin structure, a gate and a source/drain. At least one stacked fin structure is located on a substrate, wherein the stacked fin structure includes a first fin layer and a second fin layer, and a fin dielectric layer is sandwiched by the first fin layer and the second fin layer. The gate is disposed over the stacked fin structure. The source/drain is disposed directly on the substrate and directly on sidewalls of the whole stacked fin structure. The present invention provides a semiconductor process formed said semiconductor structure.

Abstract: A semiconductor structure includes at least one stacked fin structure, a gate and a source/drain. At least one stacked fin structure is located on a substrate, wherein the stacked fin structure includes a first fin layer and a second fin layer, and a fin dielectric layer is sandwiched by the first fin layer and the second fin layer. The gate is disposed over the stacked fin structure. The source/drain is disposed directly on the substrate and directly on sidewalls of the whole stacked fin structure. The present invention provides a semiconductor process formed said semiconductor structure.