Patents by Inventor Kailash Gopalakrishnan

Kailash Gopalakrishnan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8860095
    Abstract: An electronic circuit, includes a plurality of electronic devices configured as interconnected to provide one or more circuit functions and at least one interconnect structure that includes a first patterned conductor connected to a terminal of a first electronic device in the electronic circuit. A second patterned conductor is connected to a terminal of a second electronic device in the electronic circuit. A first electrode is connected to a portion of the first patterned conductor, and a second electrode is connected to a portion of the second patterned conductor. A metal oxide region is formed between the first electrode and the second electrode. The metal oxide region provides a reprogrammable switch function between the first patterned conductor and the second patterned conductor by providing a conductivity that is selectively controlled by a direction and an amount of current that passes through the metal oxide region during a switch setting operation for the metal oxide region.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: October 14, 2014
    Assignee: International Business Machines Corporation
    Inventors: Stephen M. Gates, Daniel C. Edelstein, Kailash Gopalakrishnan, Ramachandran Muralidhar
  • Patent number: 8842491
    Abstract: A system and method for operating a unipolar memory cell array including a bidirectional access diode. The system includes a column voltage switch electrically coupled to a plurality of column voltages. The column voltage switch includes an output electrically coupled to the bidirectional access diode. The plurality of column voltages includes at least one select column voltage and one deselect column voltage. The system includes a row voltage switch electrically coupled to a plurality of row voltages. The row voltage switch includes an output electrically coupled to the bidirectional access diode. The plurality of row voltages includes at least one select row voltage and one deselect row voltage. The system includes a column and row decoder electrically coupled to a select line of the column and row voltage switches, respectively.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: September 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kailash Gopalakrishnan, Chung H. Lam, Jing Li, Robert K. Montoye
  • Patent number: 8830725
    Abstract: A crystalline semiconductor Schottky barrier-like diode sandwiched between two conducting electrodes is in series with a memory element, a word line and a bit line, wherein the setup provides voltage margins greater than 1V and current densities greater than 5×106 A/cm2. This Schottky barrier-like diode can be fabricated under conditions compatible with low-temperature BEOL semiconductor processing, can supply high currents at low voltages, exhibits high on-off ratios, and enables large memory arrays.
    Type: Grant
    Filed: August 15, 2011
    Date of Patent: September 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: Donald S Bethune, Kailash Gopalakrishnan, Andrew J Kellock, Rohit S Shenoy, Kumar R Virwani
  • Patent number: 8817533
    Abstract: A crosspoint array has been shown having a plurality of bitlines and wordlines; and a plurality of crossbar elements, with each crossbar element being disposed between a bitline and a wordline and with each crossbar element having at least a solid electrolyte material used as a rectifier in series with a symmetric or substantially symmetric resistive memory node. The crossbar elements are responsive to the following voltages: a first set of voltages to transition the solid electrolyte in the crossbar elements from an OFF state to an ON state, a second set of voltages to read or program the symmetric resistive memory, and a third set of voltages to transition solid electrolyte from an ON state to an OFF state.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: August 26, 2014
    Assignee: International Business Machines Corporation
    Inventor: Kailash Gopalakrishnan
  • Patent number: 8811060
    Abstract: A device for use with a memory cross-point array of elements, each of which comprises a selection device in series with a state-holding device, in one embodiment includes a controller, configured to apply at least one voltage and/or current pulse to a selected one or more of the elements, said selected one or more of the elements including a partially- or completely-shorted selection device, so that said partially- or completely-shorted selection device passes enough current so as to damage its corresponding state-holding device and place said corresponding state-holding device in a highly resistive state, while any other selection device that is not partially- or completely-shorted passes less current so that the state-holding device corresponding to said other selection device remains unaffected. Additional systems and methods are also presented.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: August 19, 2014
    Assignee: International Business Machines Corporation
    Inventors: Geoffrey W. Burr, Rohit S. Shenoy, Kailash Gopalakrishnan
  • Publication number: 20140225165
    Abstract: An electronic circuit, includes a plurality of electronic devices configured as interconnected to provide one or more circuit functions and at least one interconnect structure that includes a first patterned conductor connected to a terminal of a first electronic device in the electronic circuit. A second patterned conductor is connected to a terminal of a second electronic device in the electronic circuit. A first electrode is connected to a portion of the first patterned conductor, and a second electrode is connected to a portion of the second patterned conductor. A metal oxide region is formed between the first electrode and the second electrode. The metal oxide region provides a reprogrammable switch function between the first patterned conductor and the second patterned conductor by providing a conductivity that is selectively controlled by a direction and an amount of current that passes through the metal oxide region during a switch setting operation for the metal oxide region.
    Type: Application
    Filed: February 13, 2013
    Publication date: August 14, 2014
    Applicant: International Business Machines Corporation
    Inventors: Stephen M. Gates, Daniel C. Edelstein, Kailash Gopalakrishnan, Ramachandran Muralidhar
  • Patent number: 8755213
    Abstract: A system and method for operating a bipolar memory cell array including a bidirectional access diode. The system includes a column voltage. The column voltage switch includes column voltages and an output electrically coupled to the bidirectional access diode. The column voltages include at least one write-one column voltage and at least one write-zero column voltage. The system also includes a row voltage switch. The row voltage switch includes row voltages and an output electrically coupled to the bidirectional access diode. The row voltages include at least one write-one row voltage and at least one write-zero row voltage. The system further includes a column decoder and a row decoder electrically coupled to a select line of the column voltage switch and row voltage switch, respectively. The system includes a write driver electrically coupled to the select lines of the row and column switches.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: June 17, 2014
    Assignee: International Business Machines Corporation
    Inventors: John K. DeBrosse, Kailash Gopalakrishnan, Chung H. Lam, Jing Li
  • Publication number: 20140022850
    Abstract: A system and method for operating a unipolar memory cell array including a bidirectional access diode. The system includes a column voltage switch electrically coupled to a plurality of column voltages. The column voltage switch includes an output electrically coupled to the bidirectional access diode. The plurality of column voltages includes at least one select column voltage and one deselect column voltage. The system includes a row voltage switch electrically coupled to a plurality of row voltages. The row voltage switch includes an output electrically coupled to the bidirectional access diode. The plurality of row voltages includes at least one select row voltage and one deselect row voltage. The system includes a column and row decoder electrically coupled to a select line of the column and row voltage switches, respectively.
    Type: Application
    Filed: July 17, 2012
    Publication date: January 23, 2014
    Applicant: International Business Machines Corporation
    Inventors: Kailash Gopalakrishnan, Chung H. Lam, Jing Li, Robert K. Montoye
  • Publication number: 20140022851
    Abstract: A system and method for operating a unipolar memory cell array including a bidirectional access diode. An example embodiment is a method including determining if the operating state of the unipolar memory cell is in a select state or a deselect state and the programming state is a read state or a write state. The method switches a column voltage switch based on the operating state and the programming state of the unipolar memory cell. The method further switches a row voltage switch based on the operating state and the programming state of the unipolar memory cell.
    Type: Application
    Filed: August 13, 2012
    Publication date: January 23, 2014
    Applicant: International Business Machines Corporation
    Inventors: Kailash Gopalakrishnan, Chung H. Lam, Jing Li, Robert K. Montoye
  • Publication number: 20130322153
    Abstract: A device for use with a memory cross-point array of elements, each of which comprises a selection device in series with a state-holding device, in one embodiment includes a controller, configured to apply at least one voltage and/or current pulse to a selected one or more of the elements, said selected one or more of the elements including a partially- or completely-shorted selection device, so that said partially- or completely-shorted selection device passes enough current so as to damage its corresponding state-holding device and place said corresponding state-holding device in a highly resistive state, while any other selection device that is not partially- or completely-shorted passes less current so that the state-holding device corresponding to said other selection device remains unaffected. Additional systems and methods are also presented.
    Type: Application
    Filed: May 31, 2012
    Publication date: December 5, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Geoffrey W. Burr, Kailash Gopalakrishnan, Rohit S. Shenoy
  • Patent number: 8552414
    Abstract: An electronically scannable multiplexing device is capable of addressing multiple bits within a volatile or non-volatile memory cell. The multiplexing device generates an electronically scannable conducting channel with two oppositely formed depletion regions. The depletion width of each depletion region is controlled by a voltage applied to a respective control gate at each end of the multiplexing device. The present multi-bit addressing technique allows, for example, 10 to 100 bits of data to be accessed or addressed at a single node. The present invention can also be used to build a programmable nanoscale logic array or for randomly accessing a nanoscale sensor array.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: October 8, 2013
    Assignee: International Business Machines Corporation
    Inventors: Hemantha Kumar Wickramasinghe, Kailash Gopalakrishnan
  • Publication number: 20130223125
    Abstract: A system and method for operating a bipolar memory cell array including a bidirectional access diode. The system includes a column voltage. The column voltage switch includes column voltages and an output electrically coupled to the bidirectional access diode. The column voltages include at least one write-one column voltage and at least one write-zero column voltage. The system also includes a row voltage switch. The row voltage switch includes row voltages and an output electrically coupled to the bidirectional access diode. The row voltages include at least one write-one row voltage and at least one write-zero row voltage. The system further includes a column decoder and a row decoder electrically coupled to a select line of the column voltage switch and row voltage switch, respectively. The system includes a write driver electrically coupled to the select lines of the row and column switches.
    Type: Application
    Filed: February 29, 2012
    Publication date: August 29, 2013
    Applicant: International Business Machines Corporation
    Inventors: John K. DeBrosse, Kailash Gopalakrishnan, Chung H. Lam, Jing Li
  • Publication number: 20130044532
    Abstract: A crystalline semiconductor Schottky barrier-like diode sandwiched between two conducting electrodes is in series with a memory element, a word line and a bit line, wherein the setup provides voltage margins greater than 1V and current densities greater than 5×106 A/cm2. This Schottky barrier-like diode can be fabricated under conditions compatible with low-temperature BEOL semiconductor processing, can supply high currents at low voltages, exhibits high on-off ratios, and enables large memory arrays.
    Type: Application
    Filed: August 15, 2011
    Publication date: February 21, 2013
    Applicant: International Business Machines Corporation
    Inventors: Donald S. Bethune, Kailash Gopalakrishnan, Andrew J. Kellock, Rohit S. Shenoy, Kumar R. Virwani
  • Publication number: 20130039110
    Abstract: Memory device and method for fabricating a memory device on two layers of a semiconductor wafer. An example device includes bit lines and word lines fabricated at one layer of a semiconductor wafer and re-writable nonvolatile memory cells that include a two-terminal access device with a bidirectional voltage-current characteristics for positive and negative voltages applied at the terminals. Additionally, a drive circuit electrically coupled to the memory cells and configured to program the memory cells is fabricated at another layer of the semiconductor wafer. Another example embodiment includes a memory device where a plurality of memory arrays are fabricated at one layer of a semiconductor wafer and a plurality of drive circuits electrically coupled to the memory cells and configured to read the memory cells are fabricated at a second layer of the semiconductor wafer.
    Type: Application
    Filed: August 14, 2011
    Publication date: February 14, 2013
    Applicant: International Business Machines Corporation
    Inventors: Chung H. Lam, Jing Li, Kailash Gopalakrishnan
  • Publication number: 20120243291
    Abstract: A crosspoint array has been shown having a plurality of bitlines and wordlines; and a plurality of crossbar elements, with each crossbar element being disposed between a bitline and a wordline and with each crossbar element having at least a solid electrolyte material used as a rectifier in series with a symmetric or substantially symmetric resistive memory node. The crossbar elements are responsive to the following voltages: a first set of voltages to transition the solid electrolyte in the crossbar elements from an OFF state to an ON state, a second set of voltages to read or program the symmetric resistive memory, and a third set of voltages to transition solid electrolyte from an ON state to an OFF state.
    Type: Application
    Filed: June 4, 2012
    Publication date: September 27, 2012
    Applicant: International Business Machines Corporation
    Inventor: Kailash Gopalakrishnan
  • Patent number: 8203873
    Abstract: An asymmetrically programmed memory material (such as a solid electrolyte material) is described for use as a rectifying element for driving symmetric or substantially symmetric resistive memory elements in a crosspoint memory architecture. A solid electrolyte element (SE) has very high resistance in the OFF state and very low resistance in the ON state (because it is a metallic filament in the ON state). These attributes make it a near ideal diode. During the passage of current (during program/read/erase) of the memory element, the solid electrolyte material also programs into the low resistance state. The final state of the solid electrolyte material is reverted to a high resistance state while making sure that the final state of the memory material is the one desired.
    Type: Grant
    Filed: April 28, 2008
    Date of Patent: June 19, 2012
    Assignee: International Business Machines Corporation
    Inventor: Kailash Gopalakrishnan
  • Publication number: 20120140571
    Abstract: An electronically scannable multiplexing device is capable of addressing multiple bits within a volatile or non-volatile memory cell. The multiplexing device generates an electronically scannable conducting channel with two oppositely formed depletion regions. The depletion width of each depletion region is controlled by a voltage applied to a respective control gate at each end of the multiplexing device. The present multi-bit addressing technique allows, for example, 10 to 100 bits of data to be accessed or addressed at a single node. The present invention can also be used to build a programmable nanoscale logic array or for randomly accessing a nanoscale sensor array.
    Type: Application
    Filed: February 16, 2012
    Publication date: June 7, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hemantha Kumar WICKRAMASINGHE, Kailash GOPALAKRISHNAN
  • Patent number: 8178362
    Abstract: An electronically scannable multiplexing device is capable of addressing multiple bits within a volatile or non-volatile memory cell. The multiplexing device generates an electronically scannable conducting channel with two oppositely formed depletion regions. The depletion width of each depletion region is controlled by a voltage applied to a respective control gate at each end of the multiplexing device. The present multi-bit addressing technique allows, for example, 10 to 100 bits of data to be accessed or addressed at a single node. The present invention can also be used to build a programmable nanoscale logic array or for randomly accessing a nanoscale sensor array.
    Type: Grant
    Filed: July 20, 2010
    Date of Patent: May 15, 2012
    Assignee: International Business Machines Corporation
    Inventors: Hemantha Kumar Wickramasinghe, Kailash Gopalakrishnan
  • Patent number: 8169820
    Abstract: A crosspoint array is made up of a plurality of bitlines and wordlines and a plurality of crossbar elements, with each crossbar element being disposed between a bitline and a wordline, and each crossbar element comprising at least a phase change material used as a rectifier in series with a solid electrolyte used as an asymmetric resistive memory element. The crossbar elements are responsive to the following voltages: a first set of voltages to transition the phase change material in the crossbar elements from an OFF state to an ON state; a second set of voltages to read or program the solid electrolyte, and a third set of voltages to transition the phase change material from an ON state to an OFF state.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: May 1, 2012
    Assignee: International Business Machines Corporation
    Inventor: Kailash Gopalakrishnan
  • Patent number: 8114723
    Abstract: A structure, memory devices using the structure, and methods of fabricating the structure. The structure includes: an array of nano-fins, each nano-fin comprising an elongated block of semiconductor material extending axially along a first direction, the nano-fins arranged in groups of at least two nano-fins each, wherein ends of nano-fins of each adjacent group of nano-fins are staggered with respect to each other on both a first and a second side of the array; wherein nano-fins of each group of nano-fins are electrically connected to a common contact that is specific to each group of nano-fins such that the common contacts comprise a first common contact on the first side of the array and a second common contact on the second side of the array; and wherein each group of nano-fins has at least two gates that electrically control the conductance of nano-fins of the each group of nano-fins.
    Type: Grant
    Filed: June 7, 2010
    Date of Patent: February 14, 2012
    Assignee: International Business Machines Corporation
    Inventors: Kailash Gopalakrishnan, Rohit Sudhir Shenoy