Abstract: Device architectures based on trapping and de-trapping holes or electrons and/or recombination of both types of carriers are obtained by carrier trapping either in near-interface deep ambipolar states or in quantum wells/dots, either serving as ambipolar traps in semiconductor layers or in gate dielectric/barrier layers. In either case, the potential barrier for trapping is small and retention is provided by carrier confinement in the deep trap states and/or quantum wells/dots. The device architectures are usable as three terminal or two terminal devices.

Abstract: A dense binary memory switch device combines the function of a pass transistor and a memory cell and has low programming and operation voltages. The device includes a charge storage region coupled to a gate electrode through a gate dielectric layer and to a channel region through a tunneling dielectric layer. The charge storage region includes a floating gate charged by tunneled carriers from the channel region. Charge retention is facilitated by the band offset between the charge storage region and the tunneling dielectric layer.

Abstract: A dense binary memory switch device combines the function of a pass transistor and a memory cell and has low programming and operation voltages. The device includes a charge storage region coupled to a gate electrode through a gate dielectric layer and directly contacting a channel region. The charge storage region contains quantum structures, deep traps or combinations thereof and is charged by carriers injected from injection regions that are in direct contact with the charge storage region. Fabrication of the device at low temperatures compatible with back-end-of-line processing is further disclosed.

Abstract: A dense binary memory switch device combines the function of a pass transistor and a memory cell and has low programming and operation voltages. The device includes a charge storage region coupled to a gate electrode through a gate dielectric layer and to a channel region through another dielectric layer. The charge storage region is charged by carriers injected from injection regions that are in direct contact with the charge storage region. Fabrication of the device at low temperatures compatible with back-end-of-line processing is further disclosed.

Abstract: Device architectures based on trapping and de-trapping holes or electrons and/or recombination of both types of carriers are obtained by carrier trapping either in near-interface deep ambipolar states or in quantum wells/dots, either serving as ambipolar traps in semiconductor layers or in gate dielectric/barrier layers. In either case, the potential barrier for trapping is small and retention is provided by carrier confinement in the deep trap states and/or quantum wells/dots. The device architectures are usable as three terminal or two terminal devices.

Abstract: Device architectures based on trapping and de-trapping holes or electrons and/or recombination of both types of carriers are obtained by carrier trapping either in near-interface deep ambipolar states or in quantum wells/dots, either serving as ambipolar traps in semiconductor layers or in gate dielectric/barrier layers. In either case, the potential barrier for trapping is small and retention is provided by carrier confinement in the deep trap states and/or quantum wells/dots. The device architectures are usable as three terminal or two terminal devices.

Abstract: A dense binary memory switch device combines the function of a pass transistor and a memory cell and has low programming and operation voltages. The device includes a charge storage region coupled to a gate electrode through a gate dielectric layer and to a channel region through a tunneling dielectric layer. The charge storage region includes a floating gate charged by tunneled carriers from the channel region. Charge retention is facilitated by the band offset between the charge storage region and the tunneling dielectric layer.

Abstract: A dense binary memory switch device combines the function of a pass transistor and a memory cell and has low programming and operation voltages. The device includes a charge storage region coupled to a gate electrode through a gate dielectric layer and to a channel region through another dielectric layer. The charge storage region is charged by carriers injected from injection regions that are in direct contact with the charge storage region. Fabrication of the device at low temperatures compatible with back-end-of-line processing is further disclosed.

Abstract: Device architectures based on trapping and de-trapping holes or electrons and/or recombination of both types of carriers are obtained by carrier trapping either in near-interface deep ambipolar states or in quantum wells/dots, either serving as ambipolar traps in semiconductor layers or in gate dielectric/barrier layers. In either case, the potential barrier for trapping is small and retention is provided by carrier confinement in the deep trap states and/or quantum wells/dots. The device architectures are usable as three terminal or two terminal devices.

Abstract: Device architectures based on trapping and de-trapping holes or electrons and/or recombination of both types of carriers are obtained by carrier trapping either in near-interface deep ambipolar states or in quantum wells/dots, either serving as ambipolar traps in semiconductor layers or in gate dielectric/barrier layers. In either case, the potential barrier for trapping is small and retention is provided by carrier confinement in the deep trap states and/or quantum wells/dots. The device architectures are usable as three terminal or two terminal devices.

Abstract: A dense binary memory switch device combines the function of a pass transistor and a memory cell and has low programming and operation voltages. The device includes a charge storage region coupled to a gate electrode through a gate dielectric layer and directly contacting a channel region. The charge storage region contains quantum structures, deep traps or combinations thereof and is charged by carriers injected from injection regions that are in direct contact with the charge storage region. Fabrication of the device at low temperatures compatible with back-end-of-line processing is further disclosed.

Abstract: Device architectures based on trapping and de-trapping holes or electrons and/or recombination of both types of carriers are obtained by carrier trapping either in near-interface deep ambipolar states or in quantum wells/dots, either serving as ambipolar traps in semiconductor layers or in gate dielectric/barrier layers. In either case, the potential barrier for trapping is small and retention is provided by carrier confinement in the deep trap states and/or quantum wells/dots. The device architectures are usable as three terminal or two terminal devices.

Abstract: A system and method for operating a unipolar memory cell array including a bidirectional access diode. An example embodiment is a method including determining if the operating state of the unipolar memory cell is in a select state or a deselect state and the programming state is a read state or a write state. The method switches a column voltage switch based on the operating state and the programming state of the unipolar memory cell. The method further switches a row voltage switch based on the operating state and the programming state of the unipolar memory cell.

Abstract: Memory device and method for fabricating a memory device on two layers of a semiconductor wafer. An example device includes bit lines and word lines fabricated at one layer of a semiconductor wafer and re-writable nonvolatile memory cells that include a two-terminal access device with a bidirectional voltage-current characteristics for positive and negative voltages applied at the terminals. Additionally, a drive circuit electrically coupled to the memory cells and configured to program the memory cells is fabricated at another layer of the semiconductor wafer. Another example embodiment includes a memory device where a plurality of memory arrays are fabricated at one layer of a semiconductor wafer and a plurality of drive circuits electrically coupled to the memory cells and configured to read the memory cells are fabricated at a second layer of the semiconductor wafer.

Abstract: An electronic circuit, includes a plurality of electronic devices configured as interconnected to provide one or more circuit functions and at least one interconnect structure that includes a first patterned conductor connected to a terminal of a first electronic device in the electronic circuit. A second patterned conductor is connected to a terminal of a second electronic device in the electronic circuit. A first electrode is connected to a portion of the first patterned conductor, and a second electrode is connected to a portion of the second patterned conductor. A metal oxide region is formed between the first electrode and the second electrode. The metal oxide region provides a reprogrammable switch function between the first patterned conductor and the second patterned conductor by providing a conductivity that is selectively controlled by a direction and an amount of current that passes through the metal oxide region during a switch setting operation for the metal oxide region.

Abstract: A system and method for operating a unipolar memory cell array including a bidirectional access diode. The system includes a column voltage switch electrically coupled to a plurality of column voltages. The column voltage switch includes an output electrically coupled to the bidirectional access diode. The plurality of column voltages includes at least one select column voltage and one deselect column voltage. The system includes a row voltage switch electrically coupled to a plurality of row voltages. The row voltage switch includes an output electrically coupled to the bidirectional access diode. The plurality of row voltages includes at least one select row voltage and one deselect row voltage. The system includes a column and row decoder electrically coupled to a select line of the column and row voltage switches, respectively.

Abstract: A crystalline semiconductor Schottky barrier-like diode sandwiched between two conducting electrodes is in series with a memory element, a word line and a bit line, wherein the setup provides voltage margins greater than 1V and current densities greater than 5×106 A/cm2. This Schottky barrier-like diode can be fabricated under conditions compatible with low-temperature BEOL semiconductor processing, can supply high currents at low voltages, exhibits high on-off ratios, and enables large memory arrays.

Abstract: A crosspoint array has been shown having a plurality of bitlines and wordlines; and a plurality of crossbar elements, with each crossbar element being disposed between a bitline and a wordline and with each crossbar element having at least a solid electrolyte material used as a rectifier in series with a symmetric or substantially symmetric resistive memory node. The crossbar elements are responsive to the following voltages: a first set of voltages to transition the solid electrolyte in the crossbar elements from an OFF state to an ON state, a second set of voltages to read or program the symmetric resistive memory, and a third set of voltages to transition solid electrolyte from an ON state to an OFF state.

Abstract: A device for use with a memory cross-point array of elements, each of which comprises a selection device in series with a state-holding device, in one embodiment includes a controller, configured to apply at least one voltage and/or current pulse to a selected one or more of the elements, said selected one or more of the elements including a partially- or completely-shorted selection device, so that said partially- or completely-shorted selection device passes enough current so as to damage its corresponding state-holding device and place said corresponding state-holding device in a highly resistive state, while any other selection device that is not partially- or completely-shorted passes less current so that the state-holding device corresponding to said other selection device remains unaffected. Additional systems and methods are also presented.

Abstract: An electronic circuit, includes a plurality of electronic devices configured as interconnected to provide one or more circuit functions and at least one interconnect structure that includes a first patterned conductor connected to a terminal of a first electronic device in the electronic circuit. A second patterned conductor is connected to a terminal of a second electronic device in the electronic circuit. A first electrode is connected to a portion of the first patterned conductor, and a second electrode is connected to a portion of the second patterned conductor. A metal oxide region is formed between the first electrode and the second electrode. The metal oxide region provides a reprogrammable switch function between the first patterned conductor and the second patterned conductor by providing a conductivity that is selectively controlled by a direction and an amount of current that passes through the metal oxide region during a switch setting operation for the metal oxide region.