Patents by Inventor Kalyan KOLLURU
Kalyan KOLLURU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240145471Abstract: Gate-all-around structures having devices with source/drain-to-substrate electrical contact are described. An integrated circuit structure includes a first vertical arrangement of horizontal nanowires above a first fin. A first gate stack is over the first vertical arrangement of horizontal nanowires. A first pair of epitaxial source or drain structures is at first and second ends of the first vertical arrangement of horizontal nanowires. One or both of the first pair of epitaxial source or drain structures is directly electrically coupled to the first fin. A second vertical arrangement of horizontal nanowires is above a second fin. A second gate stack is over the second vertical arrangement of horizontal nanowires. A second pair of epitaxial source or drain structures is at first and second ends of the second vertical arrangement of horizontal nanowires. Both of the second pair of epitaxial source or drain structures is electrically isolated from the second fin.Type: ApplicationFiled: January 9, 2024Publication date: May 2, 2024Inventors: Biswajeet GUHA, William HSU, Chung-Hsun LIN, Kinyip PHOA, Oleg GOLONZKA, Tahir GHANI, Kalyan KOLLURU, Nathan JACK, Nicholas THOMSON, Ayan KAR, Benjamin ORR
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Patent number: 11908856Abstract: Gate-all-around structures having devices with source/drain-to-substrate electrical contact are described. An integrated circuit structure includes a first vertical arrangement of horizontal nanowires above a first fin. A first gate stack is over the first vertical arrangement of horizontal nanowires. A first pair of epitaxial source or drain structures is at first and second ends of the first vertical arrangement of horizontal nanowires. One or both of the first pair of epitaxial source or drain structures is directly electrically coupled to the first fin. A second vertical arrangement of horizontal nanowires is above a second fin. A second gate stack is over the second vertical arrangement of horizontal nanowires. A second pair of epitaxial source or drain structures is at first and second ends of the second vertical arrangement of horizontal nanowires. Both of the second pair of epitaxial source or drain structures is electrically isolated from the second fin.Type: GrantFiled: December 18, 2019Date of Patent: February 20, 2024Assignee: Intel CorporationInventors: Biswajeet Guha, William Hsu, Chung-Hsun Lin, Kinyip Phoa, Oleg Golonzka, Tahir Ghani, Kalyan Kolluru, Nathan Jack, Nicholas Thomson, Ayan Kar, Benjamin Orr
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Publication number: 20240055497Abstract: Gate-all-around integrated circuit structures having adjacent deep via substrate contact for sub-fin electrical contact are described. For example, an integrated circuit structure includes a conductive via on a semiconductor substrate. A vertical arrangement of horizontal nanowires is above a fin protruding from the semiconductor substrate. A channel region of the vertical arrangement of horizontal nanowires is electrically isolated from the fin. The fin is electrically coupled to the conductive via. A gate stack is over the vertical arrangement of horizontal nanowires.Type: ApplicationFiled: October 24, 2023Publication date: February 15, 2024Inventors: Biswajeet GUHA, William HSU, Chung-Hsun LIN, Kinyip PHOA, Oleg GOLONZKA, Tahir GHANI, Kalyan KOLLURU, Nathan JACK, Nicholas THOMSON, Ayan KAR, Benjamin ORR
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Publication number: 20240038889Abstract: Gate-all-around integrated circuit structures having devices with channel-to-substrate electrical contact are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires above a first fin. A channel region of the first vertical arrangement of horizontal nanowires is electrically coupled to the first fin by a semiconductor material layer directly between the first vertical arrangement of horizontal nanowires and the first fin. A first gate stack is over the first vertical arrangement of horizontal nanowires. A second vertical arrangement of horizontal nanowires is above a second fin. A channel region of the second vertical arrangement of horizontal nanowires is electrically isolated from the second fin. A second gate stack is over the second vertical arrangement of horizontal nanowires.Type: ApplicationFiled: October 12, 2023Publication date: February 1, 2024Inventors: Biswajeet GUHA, William HSU, Chung-Hsun LIN, Kinyip PHOA, Oleg GOLONZKA, Ayan KAR, Nicholas THOMSON, Benjamin ORR, Nathan JACK, Kalyan KOLLURU, Tahir GHANI
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Patent number: 11869987Abstract: Gate-all-around integrated circuit structures including varactors are described. For example, an integrated circuit structure includes a varactor structure on a semiconductor substrate. The varactor structure includes a plurality of discrete vertical arrangements of horizontal nanowires. A plurality of gate stacks is over and surrounding corresponding ones of the plurality of discrete vertical arrangements of horizontal nanowires. The integrated circuit structure also includes a tap structure adjacent to the varactor structure on the semiconductor substrate. The tap structure includes a plurality of merged vertical arrangements of horizontal nanowires. A plurality of semiconductor structures is over and surrounding corresponding ones of the plurality of merged vertical arrangements of horizontal nanowires.Type: GrantFiled: July 7, 2022Date of Patent: January 9, 2024Assignee: Intel CorporationInventors: Ayan Kar, Saurabh Morarka, Carlos Nieva-Lozano, Kalyan Kolluru, Biswajeet Guha, Chung-Hsun Lin, Brian Greene, Tahir Ghani
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Patent number: 11837641Abstract: Gate-all-around integrated circuit structures having adjacent deep via substrate contact for sub-fin electrical contact are described. For example, an integrated circuit structure includes a conductive via on a semiconductor substrate. A vertical arrangement of horizontal nanowires is above a fin protruding from the semiconductor substrate. A channel region of the vertical arrangement of horizontal nanowires is electrically isolated from the fin. The fin is electrically coupled to the conductive via. A gate stack is over the vertical arrangement of horizontal nanowires.Type: GrantFiled: December 18, 2019Date of Patent: December 5, 2023Assignee: Intel CorporationInventors: Biswajeet Guha, William Hsu, Chung-Hsun Lin, Kinyip Phoa, Oleg Golonzka, Tahir Ghani, Kalyan Kolluru, Nathan Jack, Nicholas Thomson, Ayan Kar, Benjamin Orr
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Patent number: 11824116Abstract: Gate-all-around integrated circuit structures having devices with channel-to-substrate electrical contact are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires above a first fin. A channel region of the first vertical arrangement of horizontal nanowires is electrically coupled to the first fin by a semiconductor material layer directly between the first vertical arrangement of horizontal nanowires and the first fin. A first gate stack is over the first vertical arrangement of horizontal nanowires. A second vertical arrangement of horizontal nanowires is above a second fin. A channel region of the second vertical arrangement of horizontal nanowires is electrically isolated from the second fin. A second gate stack is over the second vertical arrangement of horizontal nanowires.Type: GrantFiled: December 18, 2019Date of Patent: November 21, 2023Assignee: Intel CorporationInventors: Biswajeet Guha, William Hsu, Chung-Hsun Lin, Kinyip Phoa, Oleg Golonzka, Ayan Kar, Nicholas Thomson, Benjamin Orr, Nathan Jack, Kalyan Kolluru, Tahir Ghani
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Publication number: 20230317850Abstract: Embodiments described herein may be related to creating a low resistance electrical path within a transistor between a front side trench connector and back side contacts and/or metal layers of the transistor. The low resistance electrical path does not go through a fin of the transistor that includes epitaxial material, but rather may go through a conductive path that does not include an epitaxial material. Embodiments may be compatible with a self-aligned back side contact architecture, which does not rely on deep via patterning. Other embodiments may be described and/or shown.Type: ApplicationFiled: March 31, 2022Publication date: October 5, 2023Inventors: Shaun MILLS, Ehren MANNEBACH, Joseph D'SILVA, Kalyan KOLLURU, Mauro J. KOBRINSKY
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Patent number: 11652107Abstract: Embodiments include diode devices and transistor devices. A diode device includes a first fin region over a first conductive region and an insulator region, and a second fin region over a second conductive and insulator regions, where the second fin region is laterally adjacent to the first fin region, and the insulator region is between the first and second conductive regions. The diode device includes a first conductive via on the first conductive region, where the first conductive via is vertically adjacent to the first fin region, and a second conductive via on the second conductive region, where the second conductive via is vertically adjacent to the second fin region. The diode device may include conductive contacts, first portions on the first fin region, second portions on the second fin region, and gate electrodes between the first and second portions and the conductive contacts.Type: GrantFiled: June 20, 2019Date of Patent: May 16, 2023Assignee: Intel CorporationInventors: Nicholas Thomson, Ayan Kar, Kalyan Kolluru, Nathan Jack, Rui Ma, Mark Bohr, Rishabh Mehandru, Halady Arpit Rao
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Publication number: 20220415877Abstract: A semiconductor device includes a first interconnect and a second interconnect, a substrate between the first and second interconnects and one or more wells on the substrate on a first level. A second level includes a first fin and a second fin, each on the one or more wells, where the first fin and the one or more wells include dopants of a first conductivity type and the second fin includes a dopant of a second conductivity type. A third fin is over a first region between the substrate and the first interconnect, and a fourth fin is over a second region between the substrate and the second interconnect. A third interconnect is electrically coupled between the first interconnect and the first fin and a fourth interconnect is electrically coupled between the second interconnect and the second fin.Type: ApplicationFiled: June 25, 2021Publication date: December 29, 2022Applicant: Intel CorporationInventors: Benjamin Orr, Rohit Grover, Nathan Jack, Nicholas Thomson, Rui Ma, Ayan Kar, Kalyan Kolluru
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Publication number: 20220415880Abstract: Substrate-less diode, bipolar and feedthrough integrated circuit structures, and methods of fabricating substrate-less diode, bipolar and feedthrough integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a semiconductor structure. A plurality of gate structures is over the semiconductor structure. A plurality of P-type epitaxial structures is over the semiconductor structure. A plurality of N-type epitaxial structures is over the semiconductor structure. One or more open locations is between corresponding ones of the plurality of gate structures. A backside contact is connected directly to one of the pluralities of P-type and N-type epitaxial structures.Type: ApplicationFiled: June 24, 2021Publication date: December 29, 2022Inventors: Ayan KAR, Kalyan KOLLURU, Nicholas THOMSON, Rui MA, Benjamin ORR, Nathan JACK, Mauro KOBRINSKY, Patrick MORROW, Chung-Hsun LIN
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Publication number: 20220415925Abstract: Substrate-less lateral diode integrated circuit structures, and methods of fabricating substrate-less lateral diode integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a fin or a stack of nanowires. A plurality of P-type epitaxial structures is over the fin or stack of nanowires. A plurality of N-type epitaxial structures is over the fin or stack of nanowires. One or more spacings are in locations over the fin or stack of nanowires, a corresponding one of the one or more spacings extending between neighboring ones of the plurality of P-type epitaxial structures and the plurality of N-type epitaxial structures.Type: ApplicationFiled: June 25, 2021Publication date: December 29, 2022Inventors: Nicholas THOMSON, Kalyan KOLLURU, Ayan KAR, Rui MA, Benjamin ORR, Nathan JACK, Biswajeet GUHA, Brian GREENE, Lin HU, Chung-Hsun LIN
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Publication number: 20220416022Abstract: Substrate-less nanowire-based lateral diode integrated circuit structures, and methods of fabricating substrate-less nanowire-based lateral diode integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a stack of nanowires. A plurality of P-type epitaxial structures is over the stack of nanowires. A plurality of N-type epitaxial structures is over the stack of nanowires. One or more gate structures is over the stack of nanowires. A semiconductor material is between and in contact with vertically adjacent ones of the stack of nanowires.Type: ApplicationFiled: June 24, 2021Publication date: December 29, 2022Inventors: Nicholas THOMSON, Kalyan KOLLURU, Ayan KAR, Rui MA, Benjamin ORR, Nathan JACK, Biswajeet GUHA, Brian GREENE, Lin HU, Chung-Hsun LIN, Sabih OMAR
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Publication number: 20220415881Abstract: Substrate-less silicon controlled rectifier (SCR) integrated circuit structures, and methods of fabricating substrate-less silicon controlled rectifier (SCR) integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a first fin portion and a second fin portion that meet at a junction. A plurality of gate structures is over the first fin portion and a second fin portion. A plurality of P-type epitaxial structures and N-type epitaxial structures is between corresponding adjacent ones of the plurality of gate structures. Pairs of the P-type epitaxial structures alternate with pairs of the N-type epitaxial structures.Type: ApplicationFiled: June 24, 2021Publication date: December 29, 2022Inventors: Rui MA, Kalyan KOLLURU, Nicholas THOMSON, Ayan KAR, Benjamin ORR, Nathan JACK, Biswajeet GUHA, Brian GREENE, Chung-Hsun LIN
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Publication number: 20220344519Abstract: Gate-all-around integrated circuit structures including varactors are described. For example, an integrated circuit structure includes a varactor structure on a semiconductor substrate. The varactor structure includes a plurality of discrete vertical arrangements of horizontal nanowires. A plurality of gate stacks is over and surrounding corresponding ones of the plurality of discrete vertical arrangements of horizontal nanowires. The integrated circuit structure also includes a tap structure adjacent to the varactor structure on the semiconductor substrate. The tap structure includes a plurality of merged vertical arrangements of horizontal nanowires. A plurality of semiconductor structures is over and surrounding corresponding ones of the plurality of merged vertical arrangements of horizontal nanowires.Type: ApplicationFiled: July 7, 2022Publication date: October 27, 2022Inventors: Ayan KAR, Saurabh MORARKA, Carlos NIEVA-LOZANO, Kalyan KOLLURU, Biswajeet GUHA, Chung-Hsun LIN, Brian GREENE, Tahir GHANI
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Patent number: 11417781Abstract: Gate-all-around integrated circuit structures including varactors are described. For example, an integrated circuit structure includes a varactor structure on a semiconductor substrate. The varactor structure includes a plurality of discrete vertical arrangements of horizontal nanowires. A plurality of gate stacks is over and surrounding corresponding ones of the plurality of discrete vertical arrangements of horizontal nanowires. The integrated circuit structure also includes a tap structure adjacent to the varactor structure on the semiconductor substrate. The tap structure includes a plurality of merged vertical arrangements of horizontal nanowires. A plurality of semiconductor structures is over and surrounding corresponding ones of the plurality of merged vertical arrangements of horizontal nanowires.Type: GrantFiled: March 25, 2020Date of Patent: August 16, 2022Assignee: Intel CorporationInventors: Ayan Kar, Saurabh Morarka, Carlos Nieva-Lozano, Kalyan Kolluru, Biswajeet Guha, Chung-Hsun Lin, Brian Greene, Tahir Ghani
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Publication number: 20220102385Abstract: Substrate-free integrated circuit structures, and methods of fabricating substrate-free integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a fin, a plurality of gate structures over the fin, and a plurality of alternating P-type epitaxial structures and N-type epitaxial structures between adjacent ones of the plurality of gate structures.Type: ApplicationFiled: September 25, 2020Publication date: March 31, 2022Inventors: Biswajeet GUHA, Brian GREENE, Avyaya JAYANTHINARASIMHAM, Ayan KAR, Benjamin ORR, Chung-Hsun LIN, Curtis TSAI, Kalyan KOLLURU, Kevin FISCHER, Lin HU, Nathan JACK, Nicholas THOMSON, Rishabh MEHANDRU, Rui MA, Sabih OMAR
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Publication number: 20210305436Abstract: Gate-all-around integrated circuit structures including varactors are described. For example, an integrated circuit structure includes a varactor structure on a semiconductor substrate. The varactor structure includes a plurality of discrete vertical arrangements of horizontal nanowires. A plurality of gate stacks is over and surrounding corresponding ones of the plurality of discrete vertical arrangements of horizontal nanowires. The integrated circuit structure also includes a tap structure adjacent to the varactor structure on the semiconductor substrate. The tap structure includes a plurality of merged vertical arrangements of horizontal nanowires. A plurality of semiconductor structures is over and surrounding corresponding ones of the plurality of merged vertical arrangements of horizontal nanowires.Type: ApplicationFiled: March 25, 2020Publication date: September 30, 2021Inventors: Ayan KAR, Saurabh MORARKA, Carlos NIEVA-LOZANO, Kalyan KOLLURU, Biswajeet GUHA, Chung-Hsun LIN, Brian GREENE, Tahir GHANI
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Publication number: 20210193836Abstract: Gate-all-around integrated circuit structures having devices with channel-to-substrate electrical contact are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires above a first fin. A channel region of the first vertical arrangement of horizontal nanowires is electrically coupled to the first fin by a semiconductor material layer directly between the first vertical arrangement of horizontal nanowires and the first fin. A first gate stack is over the first vertical arrangement of horizontal nanowires. A second vertical arrangement of horizontal nanowires is above a second fin. A channel region of the second vertical arrangement of horizontal nanowires is electrically isolated from the second fin. A second gate stack is over the second vertical arrangement of horizontal nanowires.Type: ApplicationFiled: December 18, 2019Publication date: June 24, 2021Inventors: Biswajeet GUHA, William HSU, Chung-Hsun LIN, Kinyip PHOA, Oleg GOLONZKA, Ayan KAR, Nicholas THOMSON, Benjamin ORR, Nathan JACK, Kalyan KOLLURU, Tahir GHANI
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Publication number: 20210193807Abstract: Gate-all-around integrated circuit structures having adjacent deep via substrate contact for sub-fin electrical contact are described. For example, an integrated circuit structure includes a conductive via on a semiconductor substrate. A vertical arrangement of horizontal nanowires is above a fin protruding from the semiconductor substrate. A channel region of the vertical arrangement of horizontal nanowires is electrically isolated from the fin. The fin is electrically coupled to the conductive via. A gate stack is over the vertical arrangement of horizontal nanowires.Type: ApplicationFiled: December 18, 2019Publication date: June 24, 2021Inventors: Biswajeet GUHA, William HSU, Chung-Hsun LIN, Kinyip PHOA, Oleg GOLONZKA, Tahir GHANI, Kalyan KOLLURU, Nathan JACK, Nicholas THOMSON, Ayan KAR, Benjamin ORR