Patents by Inventor Kalyanasundaram Venkateswaran

Kalyanasundaram Venkateswaran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4538247
    Abstract: Decoding apparatus for an integrated circuit memory having normal rows of memory cells 10 and at least one selectively connectable redundant second row of memory cells 31 for being connected in place of one of the first rows 10 includes a redundant decoder (transistors 32, 33. . . n) connected to each of the redundant rows 31, the redundant decoder including a plurality of selectable connections (F.sub.1, F.sub.2 . . . F.sub.n) for creating an address for each of the at least one redundant rows 31; a control signal generating circuit (gates 45, 46, and 47) for generating a control signal of a first state until an address is supplied to the memory and of a second state if any of the redundant rows 31 are selected by the address, and another decoder (transistors 23 and 39) connected to receive control signal .phi..sub.C from the generating circuit for controlling normal rows 10 and the redundant row 31 in response thereto.
    Type: Grant
    Filed: January 14, 1983
    Date of Patent: August 27, 1985
    Assignee: Fairchild Research Center
    Inventor: Kalyanasundaram Venkateswaran
  • Patent number: 4485459
    Abstract: Apparatus is provided for substituting a spare column of memory cells in a byte wide memory for a defective column of cells in such memory. The apparatus includes a spare column of memory cells, an electrically conductive line 13, a spare decoder 16 for switchably connecting the line 13 to the spare column, a first fuse FSD.sub.1 between the spare column and the line 13, a series of second fuses FS controlling a series of switches T.sub.1, T.sub.2 . . . between the line 13 and corresponding sense amplifiers 11, and a series of third fuses FD, each connected between a corresponding column and the sense amplifier associated with that column. The spare column of memory cells is connected to the appropriate sense amplifier by blowing the appropriate fuse FS and supplying the necessary address information to spare decoder 16. The defective column of memory cells may be disconnected by blowing the appropriate fuse FD.
    Type: Grant
    Filed: September 20, 1982
    Date of Patent: November 27, 1984
    Assignee: Fairchild Camera & Instrument Corp.
    Inventor: Kalyanasundaram Venkateswaran
  • Patent number: 4354257
    Abstract: A sense amplifier for use with a charge coupled device in which capacitive coupled charge is employed with a flip-flop circuit to accelerate sense and readout. Operation of the amplifier is effected with two external clocks and two internally generated clocks.
    Type: Grant
    Filed: May 23, 1980
    Date of Patent: October 12, 1982
    Assignee: Fairchild Camera and Instrument Corporation
    Inventors: Ramesh C. Varshney, Kalyanasundaram Venkateswaran