Abstract: A method for selectively refreshing data in a nonvolatile memory array based on failure type detected by an error correction code. If the page is determined to be error-free, no refresh operation takes place. Otherwise, if single-error words on a page contain erased and programmed bit errors, then a refresh operation, consisting of an erase and program, takes place. The erase operation is skipped if single-error words on a page solely contain a program failure.

Abstract: A method of operating an integrated circuit (“IC”) is disclosed. The method includes identifying one or more unused or inactive resources of the IC which will not be used in a circuit design or which are inactive during operation of the IC. The method also includes enabling resources of the IC which will be used in the circuit design, and also disabling one or more unused or inactive resources of the IC from one or more power supply terminals in response to configuration values which are stored in memory cells.

Abstract: A memory circuit for holding a single binary value. A first bit cell holds one of a logical high value and a logical low value, and a second bit cell also holds one of a logical high value and a logical low value. Circuitry is provided for placing a logical high value in the first bit cell when the binary value in the memory circuit is to be a logical high value, and circuitry is provided for placing a logical high value in the second bit cell when the binary value in the memory circuit is to be a logical low value. In this manner, a logical high value exists within the memory circuit, whether the single binary value within the memory circuit is a logical high value or a logical low value. The difference between the two values of the binary value is which of the two bit cells holds the logical high value. Thus, this memory circuit can be sensed without the use of a sense amplifier.

Abstract: A memory circuit for holding a single binary value. A first bit cell holds one of a logical high value and a logical low value, and a second bit cell also holds one of a logical high value and a logical low value. Circuitry is provided for placing a logical high value in the first bit cell when the binary value in the memory circuit is to be a logical high value, and circuitry is provided for placing a logical high value in the second bit cell when the binary value in the memory circuit is to be a logical low value. In this manner, a logical high value exists within the memory circuit, whether the single binary value within the memory circuit is a logical high value or a logical low value. The difference between the two values of the binary value is which of the two bit cells holds the logical high value. Thus, this memory circuit can be sensed without the use of a sense amplifier.

Abstract: A method for selectively refreshing data in a nonvolatile memory array based on failure type detected by an error correction code. If the page is determined to be error-free, no refresh operation takes place. Otherwise, if single-error words on a page contain erased and programmed bit errors, then a refresh operation, consisting of an erase and program, takes place. The erase operation is skipped if single-error words on a page solely contain a program failure.

Abstract: A process flow for creating a non-volatile memory cell, the process flow including the steps of forming a doped well in a semiconducting portion of a substrate, forming a gate dielectric layer on top of the substrate, depositing a first polysilicon layer on top of the gate dielectric layer, patterning and etching the first polysilicon layer, selectively oxidizing the first polysilicon layer, implanting lightly-doped source/drain regions into the well, forming sidewall spacers adjacent the first polysilicon layer, implanting source/drain regions into the well, thereby forming a channel area, depositing a dielectric layer on top of the first polysilicon layer, depositing a second polysilicon layer on top of the dielectric layer, forming a masking layer on the second polysilicon layer, and etching both the second polysilicon layer and the dielectric layer using the masking layer.

Abstract: A PLD includes a plurality of logic blocks, a test circuit, and a test pin set. The logic blocks are coupled to gating circuits that selectively adjust an operating voltage for the blocks in response to control signals. During operation of the PLD, the control signals are updated in response to externally-generated signals provided to the PLD via the test pin set and routed to the logic blocks using the test circuit.

Abstract: A method of operating a programmable logic device, including the steps of enabling resources of the programmable logic device being used in a circuit design implemented by the programmable logic device, and disabling unused or inactive resources of the programmable logic device that are not being used in the circuit design. The step of disabling can include de-coupling the unused or inactive resources from one or more power supply terminals. Alternatively, the step of disabling can include regulating a supply voltage applied to the unused or inactive resources. The step of disabling can be performed in response to configuration data bits stored by the programmable logic device and/or in response to user controlled signals. The step of disabling can be initiated during design time and/or run time of the programmable logic device.

Abstract: A method of operating a programmable logic device includes the steps of using a full VDD supply voltage to operate a first set of active blocks of the programmable logic device, and using a reduced supply voltage (e.g., 0.9 VDD) to operate a second set of active blocks of the programmable logic device. A timing analysis is performed to determine the maximum available timing slack in each active block. Active blocks having a smaller timing slack are grouped in the first set, and are coupled to receive the full VDD supply voltage. Active blocks having a larger timing slack are grouped in the second set, and are coupled to receive the reduced VDD supply voltage. As a result, the active blocks in the second set exhibit reduced power consumption, without adversely affecting the overall speed of the programmable logic device.

Abstract: A method of operating a programmable logic device, including the steps of using a full VDD supply voltage to operate one or more active blocks of the programmable logic device, and using a reduced supply voltage (e.g., ½ VDD) to operate one or more inactive blocks of the programmable logic device. The full VDD supply voltage and reduced supply voltage can be provided to the blocks of the programmable logic device through high-voltage n-channel transistors. A boosted voltage, greater than VDD, is applied to the gate of an n-channel transistor to provide the full VDD supply voltage to an active block. A standby voltage, less than VDD, is applied to the gate of an n-channel transistor to provide the reduced supply voltage to an inactive block. The inactive blocks can be determined during run time and/or design time of the programmable logic device.

Abstract: It is sometimes desirable to protect a design used in a PLD from being copied. If the design is stored in a different device from the PLD and read into the PLD through a bitstream, an unencrypted bitstream could be observed and copied as it is being loaded. According to the invention, a bitstream for configuring a PLD with an encrypted design includes unencrypted words for controlling loading of the configuration bitstream and encrypted words that actually specify the design.

Abstract: A method of operating a programmable logic device, including the steps of enabling resources of the programmable logic device being used in a circuit design implemented by the programmable logic device, and disabling unused or inactive resources of the programmable logic device that are not being used in the circuit design. The step of disabling can include de-coupling the unused or inactive resources from one or more power supply terminals. Alternatively, the step of disabling can include regulating a supply voltage applied to the unused or inactive resources. The step of disabling can be performed in response to configuration data bits stored by the programmable logic device and/or in response to user controlled signals. The step of disabling can be initiated during design time and/or run time of the programmable logic device.

Abstract: A series capacitor coupling (SCC) structure is controllable to capacitively couple a data input lead of the SCC structure to an output lead of the SCC, or to de-couple the data input lead from the data output lead. An SCC is controlled by a control bit stored in an associated memory cell. A multiplexer is fashioned out of a plurality of such SCC structures such that the edges of a digital signal received on a selected one of a plurality of multiplexer data input leads is coupled through the SCC structures onto an intervening node. The edges of the digital signal on the intervening node are then latched to recreate the incoming digital signal and the latched signal is output onto a multiplexer data output lead. The multiplexer is very fast and has a low leakage current in comparison to conventional transmission gate multiplexers used in programmable logic devices.

Abstract: To prevent copying of a design implemented in a programmable logic device (PLD), the PLD itself stores a decryption key or keys loaded by the designer, and includes a decryptor for decrypting an encrypted configuration bitstream as it is loaded into the PLD. The PLD also includes logic for reading header information that indicates whether the bitstream is encrypted, and can accept both encrypted and unencrypted bitstreams. The encryption keys may be stored in non-volatile memory or backed up with a battery so that they are retained when power is removed.

Abstract: Memory cell structures and related circuitry for use in non-volatile memory devices can be fabricated utilizing standard CMOS processes, for example, 0.18 micron or 0.15 micron processes. Advantageously, the cell structures can be programmed so that a conductive path is formed between like type materials, for example, between a p-type gate and a p-type source/drain region or an n-type gate and an n-type source/drain region. Programming cells in this manner advantageously provides a programmed cell having a low, linear resistance after programming.

Abstract: Memory cell structures and related circuitry for use in non-volatile memory devices are described. The cell structures can be fabricated utilizing standard CMOS processes, e.g. sub 0.35 micron or sub 0.25 micron processes. Preferably, the cell structures can be fabricated using 0.18 micron or 0.15 micron standard CMOS processes. Advantageously, the cell structures can be programmed so that a conductive path is formed between like type materials. For example, in certain cell structures a cell is programmed by applying a programming voltage in such a way as to form a conductive path between a p-type gate and a p-type source/drain region or an n-type gate and an n-type source/drain region. Programming cells in this manner advantageously provides a programmed cell having a low, linear resistance after programming. In addition, novel charge pump circuits are provided that, in a preferred embodiment, are located “on chip” with an array of memory cells.

Abstract: A field programmable gate array (FPGA) includes a first non-volatile memory cell and a second non-volatile memory cell. Each of the two non-volatile memory cells is capable of storing at least one bit of information. The second non-volatile memory cell provides redundant storage of the information stored in the first non-volatile memory cell. A read circuit is coupled to the first non-volatile memory cell and the second non-volatile memory cell. The read circuit simultaneously reads the information stored in the first and second non-volatile memory cells, The read circuit reads the information stored in the first non-volatile memory cell even if the second non-volatile memory cell is defective or is not programmed properly. The FPGA may include a third non-volatile memory cell coupled to the read circuit, which provides redundant storage of the information stored in the first non-volatile memory cell.

Abstract: It is sometimes desirable to encrypt a design for loading into a PLD so that an attacker may not learn and copy the design as it is being copied into the PLD. According to the invention, the encrypted design is decrypted by a key or keys within the PLD that are preserved when power is removed by either being stored in nonvolatile memory or by being backed up with a battery that switches into operation when the power is removed from the PLD.

Abstract: A two-transistor flash EPROM cell for high-speed high-density PLD applications is provided. The two-transistor cell includes a storage transistor connected in series to an access transistor. The storage transistor prevents problems associated with both over-erase and punch-through, and allows for scaling of the gate length to realize 5V cell programming.

Abstract: A field programmable gate array (FPGA) contains an array of memory cells. A word line is coupled to a row of memory cells in the array. A second signal line is coupled to the row of memory cells and extends in parallel with the word line. The second signal line applies a zero voltage to the memory cells when programming a memory cell in the row of memory cells. The second signal line applies a positive voltage to the memory cells when programming a memory cell outside the row of memory cells. Each memory cell is a one-time programmable non-volatile memory cell. Each memory cell includes a storage transistor and an access transistor coupled to one another. The memory cell can be programmed by selecting a word line and a bit line associated with the memory cell being programmed. A zero voltage is applied to a third signal line coupled to the memory cell and extending parallel to the word line. A programming voltage is applied to the selected bit line to program the memory cell.