Abstract: A supply-less transmitter output termination resistor with high accuracy is presented. This termination resistor can be used for applications with high supply voltage and low voltage devices. The termination resistor is programmable and includes many parallel branches. Each branch can be turned off or on with a switch. The biasing for the switch is in such a way that it keeps the resistance of the switch constant independent of the supply voltage or the output common mode voltage. This will increase the accuracy of the termination resistor. Besides HDMI this technique can be used for many other applications.

Abstract: A supply-less transmitter output termination resistor with high accuracy is presented. This termination resistor can be used for applications with high supply voltage and low voltage devices. The termination resistor is programmable and includes many parallel branches. Each branch can be turned off or on with a switch. The biasing for the switch is in such a way that it keeps the resistance of the switch constant independent of the supply voltage or the output common mode voltage. This will increase the accuracy of the termination resistor. Besides HDMI this technique can be used for many other applications.

Abstract: A VCO circuit having low jitter and low PSS (power supply sensitivity). The VCO circuit includes a first ring oscillator stage, a second ring oscillator stage coupled to the first ring oscillator stage, and a VCO input coupled to both the first ring oscillator stage and the second ring oscillator stage for receiving a control voltage. Each of the first ring oscillator stage and the second ring oscillator stage further includes a CMOS inverter with a plurality of cross coupled transistors to implement oscillation of the VCO circuit, wherein each of the first ring oscillator stage and the second ring oscillator stage comprises a unity gain amplifier.

Abstract: A high performance CDR circuit. The circuit includes a first and second sampler, a first and second charge-pump coupled to the first and the second sampler, a capacitor coupled to the first charge pump, and a filter coupled to the second charge pump. A VCO circuit is coupled to the first charge pump and the second charge pump, wherein a path for setting a frequency is provided by the first charge pump and the capacitor, and wherein a path for phase is provided by the second charge pump, wherein a voltage of the capacitor is stable to enable the VCO to tolerate CIDs.

Abstract: A high performance CDR circuit. The circuit includes a first and second sampler, a first and second charge-pump coupled to the first and the second sampler, a capacitor coupled to the first charge pump, and a filter coupled to the second charge pump. A VCO circuit is coupled to the first charge pump and the second charge pump, wherein a path for setting a frequency is provided by the first charge pump and the capacitor, and wherein a path for phase is provided by the second charge pump, wherein a voltage of the capacitor is stable to enable the VCO to tolerate CIDs.

Abstract: A VCO circuit having low jitter and low PSS (power supply sensitivity). The VCO circuit includes a first ring oscillator stage, a second ring oscillator stage coupled to the first ring oscillator stage, and a VCO input coupled to both the first ring oscillator stage and the second ring oscillator stage for receiving a control voltage. Each of the first ring oscillator stage and the second ring oscillator stage further includes a CMOS inverter with a plurality of cross coupled transistors to implement oscillation of the VCO circuit.

Abstract: A PLL circuit having a low spur output. The PLL circuit includes a PFD (Phase-Frequency Detector), a charge-pump coupled to the PFD, an SCR (switch-capacitor resistor) coupled to the charge pump, a filter coupled to the SCR, and a VCO circuit coupled to the filter, wherein the SCR reduces an amplitude of a plurality of current pulses at an output of the charge-pump before the plurality of current pulses reach an input of the VCL circuit.

Abstract: A low phase noise CMOS voltage controlled oscillator (VCO) circuit. The VCO circuit includes a bias circuit and a VCO cell coupled to the bias circuit. The VCO cell includes a VCO output for transmitting a VCO output signal. A frequency to voltage converter is coupled to receive the VCO output signal. The frequency to voltage converter converts a frequency of the VCO output signal into a corresponding voltage output. The voltage output is coupled to control the bias circuit. The VCO cell includes a current source coupled to the bias circuit such that the voltage output from the voltage a current converter provides negative feedback to the VCO cell via the current source. The negative feedback, in turn, reduces the phase noise on the VCO output signal.

Abstract: The present invention comprises a CMOS voltage controlled oscillator (VCO) circuit for operation at frequencies of 1 GHz and above. The circuit of the present invention includes a voltage-to-current converter circuit for receiving a VCO input, a replica circuit coupled to the voltage-to-current converter circuit, and a first and second VCO cell coupled to the replica circuit. The first and second VCO cells are also coupled to one another. The circuit of the present invention also includes a VCO output for transmitting a VCO output signal. A first current source is coupled to the first VCO cell to transmit a first current from a power supply to the first VCO cell. A second current source is coupled to the second VCO cell to transmit a second current from the power supply to the second VCO cell.

Abstract: The present invention comprises a voltage controlled oscillator (VCO) circuit having high power supply noise rejection. The VCO circuit includes a VCO input for receiving a control voltage. A level shifter circuit is coupled to the VCO input. A first and second VCO cell are coupled to the level shifter circuit and are coupled to each other. The VCO circuit also includes a VCO output for transmitting a VCO output signal. A first source follower transistor is coupled to the first VCO cell to transmit a first voltage from the power supply to the first VCO cell. A second source follower transistor is coupled to the second VCO cell to transmit a second voltage from the power supply to the second VCO cell. A first and second load transistor are included in each VCO cell. They are directly coupled to receive the control voltage such that the VCO output signal is less sensitive to noise on the power supply and the VCO output signal remains stable.

Abstract: The differential MOS current-mode logic structure of the present invention is comprised of a differential MOS transistor pair and a complementary MOS (CMOS) transistor for each of the transistors comprising the differential MOS pair. The gates of the CMOS transistors are coupled to the gates of the differential MOS pair. Since the gates of the differential MOS pair receive a differential signal from the inputs, the voltage between the gate and the source, Vgs, for each of the transistors comprising the MOS differential pair is not fixed. As a result, the gain of the CMOS current-mode logic structure of the present invention is high. In addition, since the gates of the CMOS transistors are coupled to the gates of the differential MOS pair, the current for the CMOS transistors is increased when charging the node capacitance and is decreased when discharging the node capacitance.

Abstract: A voltage controlled oscillator (VCO) circuit having low sensitivity to fabrication process variation, operating temperature variation, and power supply noise. The circuit of the present invention includes a current source controller, a bias circuit, and a first and second VCO cell. The first and second VCO cells are coupled to each other and are coupled to the bias circuit. The VCO circuit of the present invention also includes a VCO output for transmitting a VCO output signal to external electronics. A bias circuit current source is coupled to the bias circuit to transmit a bias circuit current from a power supply to the bias circuit. A first current source is coupled to the first VCO cell to transmit a first current from the power supply to the first VCO cell. A second current source coupled to the second VCO cell to transmit a second current from the power supply to the second VCO cell.

Abstract: The present invention comprises a voltage controlled oscillator (VCO) circuit having high power supply noise rejection. The circuit of the present invention includes an amplifier having positive, negative, and output terminals. A VCO input is coupled to the positive terminal for receiving a control voltage. A replica circuit is coupled to the negative terminal. A replica source follower transistor is coupled to the output terminal and is also coupled to the replica circuit. The replica source follower transistor transmits a replica current from a power supply to the replica circuit and is controlled by the amplifier. The present invention also includes a first and second VCO cell. The first VCO cell and the second VCO cell are both coupled to the replica circuit and to each other and the second VCO cell includes a VCO output for transmitting a VCO output signal.

Abstract: The present invention provides a nominal temperature and process compensating bias circuit for an integrated circuit. The bias circuit comprises a current source, a pair of linear devices, and a current stage. The current source generates a bias current. The pair of linear devices includes a first linear device and a second linear device. The first and second linear devices are coupled to each other and to the current source at a common node to enable the bias current from the current source to flow through the linear devices. The current stage includes a first transistor and a second transistor with the first transistor being coupled to the first linear device at the drain node of the first transistor and the second transistor being coupled to the second linear device at the drain node of the second transistor.

Abstract: A CMOS super high speed voltage controlled oscillator (VCO) circuit that operates at frequencies of at least 3 GHz. The VCO circuit of the present invention includes a replica circuit, a first VCO cell coupled to the replica circuit, and a second VCO cell coupled to the first VCO cell and the replica circuit. A VCO output for transmitting a VCO output signal is also included. A first current source is coupled to the first VCO cell to transmit a first current from the power supply to the first VCO cell. A second current source is coupled to the second VCO cell to transmit a second current from the power supply to the second VCO cell. The first VCO cell and the second VCO cell each have respective first and second source follower load transistors coupled to the replica circuit. In addition, the first and second VCO cells, the first and second current sources, and the replica circuit are all fabricated using n-channel MOS transistors.

Abstract: The present invention comprises a noise insensitive current source circuit having a high power supply rejection ratio. The circuit of the present invention is for use with noise sensitive circuits. The circuit of the present invention includes a first reference current source, a second reference current source, and a first, second, third, and fourth transistor. The first transistor has a drain coupled to a power supply and a source coupled to a ground via the first reference current. The second transistor has a drain coupled to the power supply and a source coupled to ground via the second reference current source. The gate of the second transistor is coupled to the gate of the first transistor and to the source of the first transistor. A third transistor has a drain coupled to the power supply and a source coupled to ground via the second reference current source. The gate of the third transistor is coupled to the source of the second transistor.