Patents by Inventor Kanae Nakagawa

Kanae Nakagawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210073049
    Abstract: A barrier synchronization system, a parallel information processing apparatus, and the like are described in the embodiments. In an example, provided is a solution to reduce latency time and improve processing speed in barrier synchronization.
    Type: Application
    Filed: September 8, 2020
    Publication date: March 11, 2021
    Applicant: FUJITSU LIMITED
    Inventors: Kanae Nakagawa, MASAKI ARAI, YASUMOTO TOMITA
  • Publication number: 20210073048
    Abstract: A barrier synchronization circuit that performs barrier synchronization of a plurality of processes executed in parallel by a plurality of processing circuits, the barrier synchronization circuit includes a first determination circuit configured to determine whether the number of first processing circuits among the plurality of the processing circuits is equal to or greater than a first threshold value, the first processing circuits having completed the process, and an instruction circuit configured to instruct a second processing circuit among the plurality of the processing circuits to forcibly stop the process when it is determined that the number is equal to or greater than the first threshold value by the first determination circuit, the second processing circuit having not completed the process.
    Type: Application
    Filed: September 8, 2020
    Publication date: March 11, 2021
    Applicant: FUJITSU LIMITED
    Inventors: Kanae Nakagawa, MASAKI ARAI, YASUMOTO TOMITA
  • Patent number: 10777726
    Abstract: A thermoelectric conversion module includes a thermoelectric conversion element, a container, a heat storage material accommodated in the container, and a first heat transfer member thermally coupled to one side of the thermoelectric conversion element and thermally coupled to the heat storage material, wherein the first heat transfer member includes a portion made of a solid-solid phase transition system heat storage material having a thermal conductivity higher than a thermal conductivity of the heat storage material and having a transition temperature different from a transition temperature of the heat storage material.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: September 15, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Kanae Nakagawa, Takashi Suzuki
  • Patent number: 10537044
    Abstract: A heat dissipating component comprising: a main body formed from a first material; a heat dissipating sheet that is formed from a second material having higher thermal conductivity than the first material, that is provided at the main body, and that includes a plurality of fins thermally connected to each other at positions other than apexes and a connecting portion thermally connecting the plurality of fins to an electronic component; and a covering portion that covers at least a portion of a bottom portion of a groove between the plurality of fins.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: January 14, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Takashi Suzuki, Kanae Nakagawa
  • Publication number: 20190148616
    Abstract: A thermoelectric conversion module includes a thermoelectric conversion element, a container, a heat storage material accommodated in the container, and a first heat transfer member thermally coupled to one side of the thermoelectric conversion element and thermally coupled to the heat storage material, wherein the first heat transfer member includes a portion made of a solid-solid phase transition system heat storage material having a thermal conductivity higher than a thermal conductivity of the heat storage material and having a transition temperature different from a transition temperature of the heat storage material.
    Type: Application
    Filed: January 17, 2019
    Publication date: May 16, 2019
    Applicant: FUJITSU LIMITED
    Inventors: Kanae Nakagawa, Takashi Suzuki
  • Publication number: 20170338393
    Abstract: A thermoelectric conversion module, includes: a thermoelectric conversion device; a first container; a fin that is thermally connected to one side of the thermoelectric conversion device, has a higher thermal conductivity than the first container, and extends in a direction away from the thermoelectric conversion device in the first container; a first heat dissipation member that is thermally connected to the one side of the thermoelectric conversion device, has a higher thermal conductivity than the fin, and extends up to a side far from the thermoelectric conversion device of the fin in the first container; and a first heat storage material that is disposed in the first container and thermally connected to the fin and the first heat dissipation member.
    Type: Application
    Filed: August 10, 2017
    Publication date: November 23, 2017
    Applicant: FUJITSU LIMITED
    Inventors: Kanae Nakagawa, Takashi Suzuki
  • Publication number: 20170110386
    Abstract: A heat dissipating component including a main body formed from a first material, and a heat dissipating sheet that is formed from a second material having higher thermal conductivity than the first material, that covers the main body, and that includes a fin, and a connecting portion that is thermally connected to the fin at a position other than an apex of the fin and is also thermally connected to an electronic component.
    Type: Application
    Filed: December 27, 2016
    Publication date: April 20, 2017
    Applicant: FUJITSU LIMITED
    Inventors: Takashi Suzuki, Kanae Nakagawa
  • Publication number: 20160338228
    Abstract: A heat dissipating component comprising: a main body formed from a first material; a heat dissipating sheet that is formed from a second material having higher thermal conductivity than the first material, that is provided at the main body, and that includes a plurality of fins thermally connected to each other at positions other than apexes and a connecting portion thermally connecting the plurality of fins to an electronic component; and a covering portion that covers at least a portion of a bottom portion of a groove between the plurality of fins.
    Type: Application
    Filed: July 20, 2016
    Publication date: November 17, 2016
    Applicant: FUJITSU LIMITED
    Inventors: Takashi Suzuki, Kanae Nakagawa
  • Publication number: 20150132865
    Abstract: A semiconductor substrate is secured by suction to a rear face of a supporting face of a substrate supporting table. In this event, the thickness of the semiconductor substrate is made fixed by planarization on the rear face, and the rear face is forcibly brought into a state free from undulation by the suction to the supporting face, so that the rear face becomes a reference face for planarization of a front face. In this state, a tool is used to cut surface layers of Au projections and a resist mask on the front face, thereby planarizing the Au projections and the resist mask so that their surfaces become continuously flat. This can planarize the surfaces of fine bumps formed on the substrate at a low cost and a high speed in place of CMP.
    Type: Application
    Filed: January 20, 2015
    Publication date: May 14, 2015
    Applicant: FUJITSU LIMITED
    Inventors: Masataka Mizukoshi, Yoshiharu Ishizuki, Kanae Nakagawa, Keishiro Okamoto, Kazuo Teshirogi, Taiji Sakai
  • Patent number: 8962470
    Abstract: A semiconductor substrate is secured by suction to a rear face of a supporting face of a substrate supporting table. In this event, the thickness of the semiconductor substrate is made fixed by planarization on the rear face, and the rear face is forcibly brought into a state free from undulation by the suction to the supporting face, so that the rear face becomes a reference face for planarization of a front face. In this state, a tool is used to cut surface layers of Au projections and a resist mask on the front face, thereby planarizing the Au projections and the resist mask so that their surfaces become continuously flat. This can planarize the surfaces of fine bumps formed on the substrate at a low cost and a high speed in place of CMP.
    Type: Grant
    Filed: March 30, 2009
    Date of Patent: February 24, 2015
    Assignee: Fujitsu Limited
    Inventors: Masataka Mizukoshi, Yoshikatsu Ishizuki, Kanae Nakagawa, Keishiro Okamoto, Kazuo Teshirogi, Taiji Sakai
  • Patent number: 8479386
    Abstract: A method for manufacturing an interposer including forming a capacitor over a semiconductor substrate; forming a first resin layer with a first partial electrode buried in over the semiconductor substrate and the capacitor; cutting an upper part of the first partial electrode and the first resin layer with a cutting tool; forming a second resin layer with a second partial electrode buried in over a glass substrate with a through-electrode buried in; cutting an upper part of the second partial electrode and the second resin layer with the cutting tool; making thermal processing with the first resin layer and the second resin layer adhered to each other while connecting the first partial electrode and the second partial electrode to each other; removing the semiconductor substrate; forming a third resin layer over the glass substrate, covering the capacitor; and burying a third partial electrode in the third resin layer.
    Type: Grant
    Filed: November 12, 2010
    Date of Patent: July 9, 2013
    Assignee: Fujitsu Limited
    Inventors: Takeshi Shioga, Kazuaki Kurihara, Kanae Nakagawa, Taiji Sakai, Masataka Mizukoshi
  • Patent number: 8318599
    Abstract: The resin layer formation method comprises the step of forming on a substrate 10 a resin layer 34 for containing a substance for decreasing the thermal expansion coefficient to thereby forming a resin layer 34 having said substance localized in the side thereof nearer to the substrate 10; and the step of cutting the surface of the resin layer 34 with a cutting tool 40 to planarize the surface of the resin layer 34. The resin layer 34 as said substance for decreasing the thermal expansion coefficient localized in the side thereof nearer to the substrate 10, and the surface of the resin layer 34 is cut to planarize the surface of the resin layer 34, whereby the extreme abrasion and breakage of the cutting tool 40 by said substance for decreasing the thermal expansion coefficient can be prevented.
    Type: Grant
    Filed: May 30, 2006
    Date of Patent: November 27, 2012
    Assignee: Fujitsu Limited
    Inventors: Kanae Nakagawa, Motoaki Tani
  • Patent number: 8058110
    Abstract: The plating method comprises the step of forming a resin layer 10 over a substrate 16; the step of cutting the surface part of the resin layer 10 with a cutting tool 12; the step of forming a seed layer 36 on the resin layer 10 by electroless plating; and the step of forming a plating film 44 on the seed layer 36 by electroplating. Suitable roughness can be give to the surface of the resin layer 10, whereby the adhesion between the seed layer 36 and the resin layer 10 can be sufficiently ensured. Excessively deep pores are not formed in the surface of the resin layer 10 as are by desmearing treatment, whereby a micronized pattern of a photoresist film 40 can be formed on the resin layer 10. Thus, interconnections 44, etc. can be formed over the resin layer 10 at a narrow pitch with high reliability ensured.
    Type: Grant
    Filed: March 9, 2011
    Date of Patent: November 15, 2011
    Assignee: Fujitsu Limited
    Inventors: Masataka Mizukoshi, Kanae Nakagawa, Takeshi Shioga, Kazuaki Kurihara, John David Baniecki
  • Publication number: 20110168564
    Abstract: The plating method comprises the step of forming a resin layer 10 over a substrate 16; the step of cutting the surface part of the resin layer 10 with a cutting tool 12; the step of forming a seed layer 36 on the resin layer 10 by electroless plating; and the step of forming a plating film 44 on the seed layer 36 by electroplating. Suitable roughness can be give to the surface of the resin layer 10, whereby the adhesion between the seed layer 36 and the resin layer 10 can be sufficiently ensured. Excessively deep pores are not formed in the surface of the resin layer 10 as are by desmearing treatment, whereby a micronized pattern of a photoresist film 40 can be formed on the resin layer 10. Thus, interconnections 44, etc. can be formed over the resin layer 10 at a narrow pitch with high reliability ensured.
    Type: Application
    Filed: March 9, 2011
    Publication date: July 14, 2011
    Applicant: FUJITSU LIMITED
    Inventors: Masataka Mizukoshi, Kanae Nakagawa, Takeshi Shioga, Kazuaki Kurihara, John David Baniecki
  • Patent number: 7927998
    Abstract: The plating method comprises the step of forming a resin layer 10 over a substrate 16; the step of cutting the surface part of the resin layer 10 with a cutting tool 12; the step of forming a seed layer 36 on the resin layer 10 by electroless plating; and the step of forming a plating film 44 on the seed layer 36 by electroplating. Suitable roughness can be give to the surface of the resin layer 10, whereby the adhesion between the seed layer 36 and the resin layer 10 can be sufficiently ensured. Excessively deep pores are not formed in the surface of the resin layer 10, as are by desmearing treatment, whereby a micronized pattern of a photoresist film 40 can be formed on the resin layer 10. Thus, interconnections 44, etc. can be formed over the resin layer 10 at a narrow pitch with high reliability ensured.
    Type: Grant
    Filed: January 8, 2010
    Date of Patent: April 19, 2011
    Assignee: Fujitsu Limited
    Inventors: Masataka Mizukoshi, Kanae Nakagawa, Takeshi Shioga, Kazuaki Kurihara, John David Baniecki
  • Publication number: 20110056068
    Abstract: The interposer includes a glass substrate 46 with first through-electrodes 47 buried in; a plurality of resin layers 68, 20, 32 supported by the glass substrate; thin film capacitors 18a, 18b buried between a first resin layer 68 of the plural resin layers and a second resin layer 20 of the plural resin layers and including the first capacitor electrodes 12a, 12b, the second capacitor electrodes 16 opposed to the first capacitor electrodes 12a, 12b, and a dielectric thin film 14 of a relative dielectric constant of 200 or above formed between the first capacitor electrode 12a, 12b and the second capacitor electrode 16, and the second through-electrodes 77a, 77b penetrating the plural resin layers 68, 20, 32, electrically connected to the first through-electrode 47 and electrically connected to the first capacitor electrode 12a, 12b or the second capacitor electrode 16.
    Type: Application
    Filed: November 12, 2010
    Publication date: March 10, 2011
    Applicant: FUJITSU LIMITED
    Inventors: Takeshi Shioga, Kazuaki Kurihara, Kanae Nakagawa, Taiji Sakai, Masataka Mizukoshi
  • Patent number: 7863524
    Abstract: The interposer includes a glass substrate 46 with first through-electrodes 47 buried in; a plurality of resin layers 68, 20, 32 supported by the glass substrate; thin film capacitors 18a, 18b buried between a first resin layer 68 of the plural resin layers and a second resin layer 20 of the plural resin layers and including the first capacitor electrodes 12a, 12b, the second capacitor electrodes 16 opposed to the first capacitor electrodes 12a, 12b, and a dielectric thin film 14 of a relative dielectric constant of 200 or above formed between the first capacitor electrode 12a, 12b and the second capacitor electrode 16, and the second through-electrodes 77a, 77b penetrating the plural resin layers 68, 20, 32, electrically connected to the first through-electrode 47 and electrically connected to the first capacitor electrode 12a, 12b or the second capacitor electrode 16.
    Type: Grant
    Filed: September 20, 2007
    Date of Patent: January 4, 2011
    Assignee: Fujitsu Limited
    Inventors: Takeshi Shioga, Kazuaki Kurihara, Kanae Nakagawa, Taiji Sakai, Masataka Mizukoshi
  • Publication number: 20100112775
    Abstract: The plating method comprises the step of forming a resin layer 10 over a substrate 16; the step of cutting the surface part of the resin layer 10 with a cutting tool 12; the step of forming a seed layer 36 on the resin layer 10 by electroless plating; and the step of forming a plating film 44 on the seed layer 36 by electroplating. Suitable roughness can be give to the surface of the resin layer 10, whereby the adhesion between the seed layer 36 and the resin layer 10 can be sufficiently ensured. Excessively deep pores are not formed in the surface of the resin layer 10, as are by desmearing treatment, whereby a micronized pattern of a photoresist film 40 can be formed on the resin layer 10. Thus, interconnections 44, etc. can be formed over the resin layer 10 at a narrow pitch with high reliability ensured.
    Type: Application
    Filed: January 8, 2010
    Publication date: May 6, 2010
    Applicant: FUJITSU LIMITED
    Inventors: Masataka Mizukoshi, Kanae Nakagawa, Takeshi Shioga, Kazuaki Kurihara, John David Baniecki
  • Patent number: 7704856
    Abstract: A substrate support (201) having a flat supporting surface (201a) is prepared, and a semiconductor substrate (1) is fixed to the substrate supporting surface (201) by attaching a wiring forming surface (1a) to the supporting surface (201a) by suction, for example, by vacuum suction. On this occasion, the wiring forming surface (1a) is forcibly flattened by being attached to the supporting surface (201a) by suction, and therefore the wiring forming surface (1a) becomes a reference plane for planarization of a back surface (1b). In this state, planarization processing is performed by mechanically grinding the back surface (1b) to grind away projecting portions (12) of the back surface (1b). Hence, variations in the thickness of the substrate (especially, semiconductor substrate) are made uniform, and high-speed planarization is realized easily and inexpensively without disadvantages such as dishing and without any limitation on a wiring design.
    Type: Grant
    Filed: March 23, 2007
    Date of Patent: April 27, 2010
    Assignee: Fujitsu Limited
    Inventors: Kanae Nakagawa, Masataka Mizukoshi, Kazuo Teshirogi
  • Patent number: 7670940
    Abstract: The plating method comprises the step of forming a resin layer 10 over a substrate 16; the step of cutting the surface part of the resin layer 10 with a cutting tool 12; the step of forming a seed layer 36 on the resin layer 10 by electroless plating; and the step of forming a plating film 44 on the seed layer 36 by electroplating. Suitable roughness can be give to the surface of the resin layer 10, whereby the adhesion between the seed layer 36 and the resin layer 10 can be sufficiently ensured. Excessively deep pores are not formed in the surface of the resin layer 10, as are by desmearing treatment, whereby a micronized pattern of a photoresist film 40 can be formed on the resin layer 10. Thus, interconnections 44, etc. can be formed over the resin layer 10 at a narrow pitch with high reliability ensured.
    Type: Grant
    Filed: October 17, 2005
    Date of Patent: March 2, 2010
    Assignee: Fujitsu Limited
    Inventors: Masataka Mizukoshi, Kanae Nakagawa, Takeshi Shioga, Kazuaki Kurihara, John David Baniecki