Patents by Inventor Kaname Motoyoshi

Kaname Motoyoshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200350397
    Abstract: A high-frequency transistor includes a source electrode, a drain electrode, a gate electrode, and a gate drive line that applies a voltage to the gate electrode. An impedance adjustment circuit is connected between the gate electrode and the gate drive line. A characteristic impedance of the gate electrode is Z1, when a connecting point between the impedance adjustment circuit and the gate electrode is viewed from the impedance adjustment circuit. A characteristic impedance of the gate drive line is Z2, when a connecting point between the impedance adjustment circuit and the gate drive line is viewed from the impedance adjustment circuit. X that denotes a characteristic impedance of the impedance adjustment circuit is a value between Z1 and Z2.
    Type: Application
    Filed: July 20, 2020
    Publication date: November 5, 2020
    Inventors: Kouki YAMAMOTO, Masatoshi KAMITANI, Shingo MATSUDA, Hiroshi SUGIYAMA, Kaname MOTOYOSHI, Masao NAKAYAMA
  • Patent number: 10756165
    Abstract: A high-frequency transistor includes a source electrode, a drain electrode, a gate electrode, and a gate drive line that applies a voltage to the gate electrode. An impedance adjustment circuit is connected between the gate electrode and the gate drive line. A characteristic impedance of the gate electrode is Z1, when a connecting point between the impedance adjustment circuit and the gate electrode is viewed from the impedance adjustment circuit. A characteristic impedance of the gate drive line is Z2, when a connecting point between the impedance adjustment circuit and the gate drive line is viewed from the impedance adjustment circuit. X that denotes a characteristic impedance of the impedance adjustment circuit is a value between Z1 and Z2.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: August 25, 2020
    Assignee: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
    Inventors: Kouki Yamamoto, Masatoshi Kamitani, Shingo Matsuda, Hiroshi Sugiyama, Kaname Motoyoshi, Masao Nakayama
  • Publication number: 20190378894
    Abstract: A high-frequency transistor includes a source electrode, a drain electrode, a gate electrode, and a gate drive line that applies a voltage to the gate electrode. An impedance adjustment circuit is connected between the gate electrode and the gate drive line. A characteristic impedance of the gate electrode is Z1, when a connecting point between the impedance adjustment circuit and the gate electrode is viewed from the impedance adjustment circuit. A characteristic impedance of the gate drive line is Z2, when a connecting point between the impedance adjustment circuit and the gate drive line is viewed from the impedance adjustment circuit. X that denotes a characteristic impedance of the impedance adjustment circuit is a value between Z1 and Z2.
    Type: Application
    Filed: August 23, 2019
    Publication date: December 12, 2019
    Inventors: Kouki YAMAMOTO, Masatoshi KAMITANI, Shingo MATSUDA, Hiroshi SUGIYAMA, Kaname MOTOYOSHI, Masao NAKAYAMA
  • Patent number: 8040186
    Abstract: A bias circuit 12 includes: a transistor Q5 operable to supply, to an amplifier 11, a bias current in accordance with a base current supplied thereto; a transistor Q3 operable to pass a current in accordance with a reference voltage Vref; a transistor Q2 operable to correct, in accordance with the current passed by the transistor Q3, the base current to be supplied to the transistor Q5, so as to compensate a temperature characteristic represented by the transistor Q5; and a bias changing section (of a transistor Q4, and resistances R5, R6, and R7), connected to a base of the transistor Q5, operable to change, in accordance with a control voltage VSW, an amount of the base current to be supplied to the transistor Q5. The amplifier 11 amplifies, by using the bias current supplied by the bias circuit 12, a radio frequency signal having been inputted thereto.
    Type: Grant
    Filed: November 25, 2009
    Date of Patent: October 18, 2011
    Assignee: Panasonic Corporation
    Inventors: Masao Nakayama, Hiroshi Sugiyama, Kazuhiko Oohashi, Kouki Yamamoto, Kaname Motoyoshi
  • Publication number: 20110241783
    Abstract: Provided are a detector circuit which has a simple circuit configuration, is capable of indicating an accurate power according to a load fluctuation of a radio frequency power amplifier or a difference in a modulation mode, and can be easily incorporated in the radio frequency power amplifier, and a wireless communication system using the detector circuit. The detector circuit 10 includes a detecting resistor 11 for detecting a part of a current flowing from a bias circuit 6, and a current-voltage conversion circuit 12 for converting a current obtained through the detecting resistor 11 into a voltage.
    Type: Application
    Filed: June 20, 2011
    Publication date: October 6, 2011
    Applicant: Panasonic Corporation
    Inventors: Haruhiko KOIZUMI, Kaname Motoyoshi
  • Patent number: 7990221
    Abstract: Provided are a detector circuit which has a simple circuit configuration, is capable of indicating an accurate power according to a load fluctuation of a radio frequency power amplifier or a difference in a modulation mode, and can be easily incorporated in the radio frequency power amplifier, and a wireless communication system using the detector circuit. The detector circuit 10 includes a detecting resistor 11 for detecting a part of a current flowing from a bias circuit 6, and a current-voltage conversion circuit 12 for converting a current obtained through the detecting resistor 11 into a voltage.
    Type: Grant
    Filed: July 30, 2009
    Date of Patent: August 2, 2011
    Assignee: Panasonic Corporation
    Inventors: Haruhiko Koizumi, Kaname Motoyoshi
  • Publication number: 20110175681
    Abstract: To provide a radio frequency power amplifier that realizes a favorable high-frequency characteristic without using an isolator and also achieves low power consumption. The radio frequency power amplifier includes: a power amplifier which amplifies a radio frequency signal; a voltage supplying unit which supplies a collector voltage to the power amplifier; a current supplying unit which supplies a bias current to the power amplifier; and a bias current detecting unit which detects the bias current. The voltage supplying unit has a control unit which sets the power supply voltage at: a first voltage when the detected bias current is lower than a bias-current reference value; and a second voltage lower than the first voltage when the detected bias current is higher than the bias-current reference value.
    Type: Application
    Filed: December 17, 2010
    Publication date: July 21, 2011
    Applicant: PANASONIC CORPORATION
    Inventors: Masahiko INAMORI, Kaname MOTOYOSHI, Masao NAKAYAMA, Kouki YAMAMOTO, Tsunehiro TAKAGI, Hiroshi SUGIYAMA, Junji KAIDO
  • Patent number: 7924098
    Abstract: A first FET is inserted in a series position between a signal input terminal and a signal output terminal, while second and third FETs are inserted in a shunt position respectively between the signal input terminal and a ground terminal and between the signal output terminal and a ground terminal. First and second reference voltage terminals and a control terminal are provided. A first reference voltage and a control voltage are applied to the first FET, while a second reference voltage and a control voltage are applied respectively to the second and third FETs, so that the first, second, and third FETs serve as variable resistors. As such, a gain control circuit is constructed. Further, a first resistor is provided in parallel to the first FET, while second and third resistors are provided respectively in series to the second and third FETs.
    Type: Grant
    Filed: October 2, 2009
    Date of Patent: April 12, 2011
    Assignee: Panasonic Corporation
    Inventors: Masao Nakayama, Tsunehiro Takagi, Masahiko Inamori, Kaname Motoyoshi
  • Publication number: 20100273535
    Abstract: A radio-frequency power amplifier device includes an input terminal for which a first radio-frequency signal for a CDMA mode within a first frequency band and a third radio-frequency signal for a TDMA mode within the first frequency band are selectively provided, a second input terminal for which a second radio-frequency signal for a CDMA mode within a second frequency band and a fourth radio-frequency signal for a TDMA mode within the second frequency band are selectively provided, a first power amplifier unit which to amplifies the provided first radio-frequency signal, a second power amplifier unit which amplifies the provided second radio-frequency signal, a third power amplifier unit which amplifies the provided third radio-frequency signal, and a fourth power amplifier unit which amplifies the provided fourth radio-frequency signal. These power amplifier units are arranged in order of the first power amplifier unit to the fourth power amplifier unit.
    Type: Application
    Filed: April 13, 2010
    Publication date: October 28, 2010
    Applicant: PANASONIC CORPORATION
    Inventors: Masahiko INAMORI, Motoyoshi IWATA, Kaname MOTOYOSHI, Masahiro MAEDA, Yorito OTA
  • Publication number: 20100134189
    Abstract: A bias circuit 12 includes: a transistor Q5 operable to supply, to an amplifier 11, a bias current in accordance with a base current supplied thereto; a transistor Q3 operable to pass a current in accordance with a reference voltage Vref; a transistor Q2 operable to correct, in accordance with the current passed by the transistor Q3, the base current to be supplied to the transistor Q5, so as to compensate a temperature characteristic represented by the transistor Q5; and a bias changing section (of a transistor Q4, and resistances R5, R6, and R7), connected to a base of the transistor Q5, operable to change, in accordance with a control voltage VSW, an amount of the base current to be supplied to the transistor Q5. The amplifier 11 amplifies, by using the bias current supplied by the bias circuit 12, a radio frequency signal having been inputted thereto.
    Type: Application
    Filed: November 25, 2009
    Publication date: June 3, 2010
    Applicant: PANASONIC CORPORATION
    Inventors: Masao NAKAYAMA, Hiroshi SUGIYAMA, Kazuhiko OOHASHI, Kouki YAMAMOTO, Kaname MOTOYOSHI
  • Publication number: 20100026390
    Abstract: Provided are a detector circuit which has a simple circuit configuration, is capable of indicating an accurate power according to a load fluctuation of a radio frequency power amplifier or a difference in a modulation mode, and can be easily incorporated in the radio frequency power amplifier, and a wireless communication system using the detector circuit. The detector circuit 10 includes a detecting resistor 11 for detecting a part of a current flowing from a bias circuit 6, and a current-voltage conversion circuit 12 for converting a current obtained through the detecting resistor 11 into a voltage.
    Type: Application
    Filed: July 30, 2009
    Publication date: February 4, 2010
    Inventors: Haruhiko KOIZUMI, Kaname Motoyoshi
  • Publication number: 20100022198
    Abstract: A first FET is inserted in a series position between a signal input terminal and a signal output terminal, while second and third FETs are inserted in a shunt position respectively between the signal input terminal and a ground terminal and between the signal output terminal and a ground terminal. First and second reference voltage terminals and a control terminal are provided. A first reference voltage and a control voltage are applied to the first FET, while a second reference voltage and a control voltage are applied respectively to the second and third FETs, so that the first, second, and third FETs serve as variable resistors. As such, a gain control circuit is constructed. Further, a first resistor is provided in parallel to the first FET, while second and third resistors are provided respectively in series to the second and third FETs.
    Type: Application
    Filed: October 2, 2009
    Publication date: January 28, 2010
    Applicant: PANASONIC CORPORATION
    Inventors: Masao NAKAYAMA, Tsunehiro TAKAGI, Masahiko INAMORI, Kaname MOTOYOSHI
  • Patent number: 7639080
    Abstract: A bias circuit 12 includes: a transistor Q5 operable to supply, to an amplifier 11, a bias current in accordance with a base current supplied thereto; a transistor Q3 operable to pass a current in accordance with a reference voltage Vref; a transistor Q2 operable to correct, in accordance with the current passed by the transistor Q3, the base current to be supplied to the transistor Q5, so as to compensate a temperature characteristic represented by the transistor Q5; and a bias changing section (of a transistor Q4, and resistances R5, R6, and R7), connected to a base of the transistor Q5, operable to change, in accordance with a control voltage VSW, an amount of the base current to be supplied to the transistor Q5. The amplifier 11 amplifies, by using the bias current supplied by the bias circuit 12, a radio frequency signal having been inputted thereto.
    Type: Grant
    Filed: June 7, 2007
    Date of Patent: December 29, 2009
    Assignee: Panasonic Corporation
    Inventors: Masao Nakayama, Hiroshi Sugiyama, Kazuhiko Oohashi, Kouki Yamamoto, Kaname Motoyoshi
  • Patent number: 7626459
    Abstract: A first FET is inserted in a series position between a signal input terminal and a signal output terminal, while second and third FETs are inserted in a shunt position respectively between the signal input terminal and a ground terminal and between the signal output terminal and a ground terminal. First and second reference voltage terminals and a control terminal are provided. A first reference voltage and a control voltage are applied to the first FET, while a second reference voltage and a control voltage are applied respectively to the second and third FETs, so that the first, second, and third FETs serve as variable resistors. As such, a gain control circuit is constructed. Further, a first resistor is provided in parallel to the first FET, while second and third resistors are provided respectively in series to the second and third FETs.
    Type: Grant
    Filed: May 29, 2007
    Date of Patent: December 1, 2009
    Assignee: Panasonic Corporation
    Inventors: Masao Nakayama, Tsunehiro Takagi, Masahiko Inamori, Kaname Motoyoshi
  • Patent number: 7454182
    Abstract: A high frequency part, which amplifies a high frequency signal outputted from an intermediate frequency part and supplies to an antenna, is equipped with a gain controller with switch function. The gain controller with switch function comprises an attenuator with switch function has a function of switching a selected band between two bands outputted from the intermediate frequency part and controlling the gain of the high frequency signal in the selected band. The attenuator with switch function comprises a first variable resistor which connects a signal input part with a signal output part and a second variable resistor which is disposed parallel to said first variable resistor and connects a signal input part with a signal output part. The first and the second variable resistors are controlled by a common gain control voltage and set such that the gain control voltage ranges, which are for changing the resistor values, will not overlap with each other.
    Type: Grant
    Filed: June 5, 2007
    Date of Patent: November 18, 2008
    Assignee: Panasonic Corporation
    Inventors: Masahiko Inamori, Takashi Yamamoto, Masao Nakayama, Kaname Motoyoshi
  • Patent number: 7425872
    Abstract: A bias voltage is applied via a first resistance to the base of a first transistor, and a radio frequency signal is input via a first capacitor to the base of the first transistor. The bias voltage is applied via a second resistance to the base of a second transistor. The bias voltage is applied via a third resistance to the base of a third transistor, and the radio frequency signal RF is input via a third capacitor to the base of the third transistor. A first band rejection filter is provided between the base of the first transistor and the base of the second transistor. A second band rejection filter is provided between the base of the second transistor and the base of the third transistor. The collectors of the first to third transistors are connected in common and the emitters thereof are all grounded.
    Type: Grant
    Filed: August 7, 2006
    Date of Patent: September 16, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masahiko Inamori, Kazuhiko Ohhashi, Hiroshi Sugiyama, Masao Nakayama, Kaname Motoyoshi
  • Patent number: 7421255
    Abstract: An output level of a transmission apparatus 1 is determined, depending on an attenuation amount of an attenuator 30, a gain of one of a high output level amplification section 17 and a low output level amplification section 18, which is used. A reference voltage Vref(H) is discontinuously changed. Depending on the magnitude of the reference voltage Vref(H), it is determined which of the amplification sections 17, 18 is used, and the attenuation amount of the attenuator 30 and the gain of the amplification section 17, 18 are also determined. When the magnitude of the reference voltage Vref(H) is changed, a sum of the attenuation amount of the attenuator 30 and a gain change amount of a switch amplification section 19 is substantially zero.
    Type: Grant
    Filed: July 26, 2005
    Date of Patent: September 2, 2008
    Assignee: Matsushita Electric Industrial Co., LTD
    Inventors: Masahiko Inamori, Tsunehiro Takagi, Masao Nakayama, Haruhiko Koizumi, Kaname Motoyoshi
  • Patent number: 7340229
    Abstract: A gain control circuit 12 comprises an FET 41 operating as a variable resistor. A gate terminal of the FET 41 is supplied with a control voltage VC applied to a gain control terminal 23. A source terminal and a drain terminal of the FET 41 are supplied with a reference voltage Vref1 obtained by a reference voltage circuit 13. The reference voltage Vref1 is controlled so as to compensate for a variation in the threshold voltage of the FET 41. The resistance value of the FET 41 is changed in accordance with the control voltage VC, and thus the gain of the high frequency amplification circuit 10 is also continuously changed.
    Type: Grant
    Filed: July 13, 2005
    Date of Patent: March 4, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masao Nakayama, Tsunehiro Takagi, Masahiko Inamori, Kaname Motoyoshi
  • Publication number: 20070296503
    Abstract: A bias circuit 12 includes: a transistor Q5 operable to supply, to an amplifier 11, a bias current in accordance with a base current supplied thereto; a transistor Q3 operable to pass a current in accordance with a reference voltage Vref; a transistor Q2 operable to correct, in accordance with the current passed by the transistor Q3, the base current to be supplied to the transistor Q5, so as to compensate a temperature characteristic represented by the transistor Q5; and a bias changing section (of a transistor Q4, and resistances R5, R6, and R7), connected to a base of the transistor Q5, operable to change, in accordance with a control voltage VSW, an amount of the base current to be supplied to the transistor Q5. The amplifier 11 amplifies, by using the bias current supplied by the bias circuit 12, a radio frequency signal having been inputted thereto.
    Type: Application
    Filed: June 7, 2007
    Publication date: December 27, 2007
    Inventors: Masao Nakayama, Hiroshi Sugiyama, Kazuhiko Oohashi, Kouki Yamamoto, Kaname Motoyoshi
  • Patent number: 7312661
    Abstract: A bias current to be supplied to an amplification circuit 60 is drawn out of a collector of a transistor Q11 of a bias circuit 10. The drawn-out bias current is input to a base of a transistor Q13 via an attenuation filter F2 and is output from an emitter of the transistor Q13 in the state where the voltage thereof is reduced by a level corresponding to Vbe. The attenuation filter F2 is conducted in a DC manner, and attenuates a component of a frequency fH(=2ft?fr) defined by a transmission frequency ft and a receiving frequency fr of a radio frequency signal. The bias current output from the emitter of the transistor Q13 is supplied to the amplification circuit 60 via an attenuation filter F1. The attenuation filter F1 is conducted in a DC manner, and attenuates a component of a frequency fL(=|fr?ft|).
    Type: Grant
    Filed: August 16, 2005
    Date of Patent: December 25, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kaname Motoyoshi, Masahiko Inamori, Kazuhiko Ohhashi, Hiroshi Sugiyama