Abstract: A power amplifier device includes: a first power supply terminal for inputting a first power supply voltage; a first transistor for power amplification that (i) includes a first gate to which a bias voltage is applied, and (ii) is supplied with power from the first power supply terminal; a second power supply terminal for inputting a second power supply voltage lower than the first power supply voltage; a second transistor for monitoring that (i) includes a second gate to which the bias voltage is applied, (ii) is supplied with power from the first power supply terminal or the second power supply terminal, and (iii) imitates an operation of the first transistor; and a bias circuit that is supplied with power from the second power supply terminal and generates and adjusts the bias voltage according to a drain current or a source current of the second transistor.

Abstract: A power amplifier device includes: a first power supply terminal for inputting a first power supply voltage; a first transistor for power amplification that (i) includes a first gate to which a bias voltage is applied, and (ii) is supplied with power from the first power supply terminal; a second power supply terminal for inputting a second power supply voltage lower than the first power supply voltage; a second transistor for monitoring that (i) includes a second gate to which the bias voltage is applied, (ii) is supplied with power from the first power supply terminal or the second power supply terminal, and (iii) imitates an operation of the first transistor; and a bias circuit that is supplied with power from the second power supply terminal and generates and adjusts the bias voltage according to a drain current or a source current of the second transistor.

Abstract: A power amplifier device includes: a first power supply terminal for inputting a first power supply voltage; a first transistor for power amplification that (i) includes a first gate to which a bias voltage is applied, and (ii) is supplied with power from the first power supply terminal; a second power supply terminal for inputting a second power supply voltage lower than the first power supply voltage; a second transistor for monitoring that (i) includes a second gate to which the bias voltage is applied, (ii) is supplied with power from the first power supply terminal or the second power supply terminal, and (iii) imitates an operation of the first transistor; and a bias circuit that is supplied with power from the second power supply terminal and generates and adjusts the bias voltage according to a drain current or a source current of the second transistor.

Abstract: A power amplifier device includes: a first power supply terminal for inputting a first power supply voltage; a first transistor for power amplification that (i) includes a first gate to which a bias voltage is applied, and (ii) is supplied with power from the first power supply terminal; a second power supply terminal for inputting a second power supply voltage lower than the first power supply voltage; a second transistor for monitoring that (i) includes a second gate to which the bias voltage is applied, (ii) is supplied with power from the first power supply terminal or the second power supply terminal, and (iii) imitates an operation of the first transistor; and a bias circuit that is supplied with power from the second power supply terminal and generates and adjusts the bias voltage according to a drain current or a source current of the second transistor.

Abstract: A resistive element that includes: a substrate; a first nitride semiconductor layer; a second nitride semiconductor layer; a two-dimensional electron gas layer on the first nitride semiconductor layer side at an interface between the first nitride semiconductor layer and the second nitride semiconductor layer; a first electrode ohmically connected to the two-dimensional electron gas layer; a second electrode ohmically connected to the two-dimensional electron gas layer; and an insulating layer between the first electrode and the second electrode in plan view. The two-dimensional electron gas layer functions as an electric resistance element. A conductive layer is not provided above the insulating layer between the first electrode and the second electrode in the plan view. The resistive element has a resistance-value stabilization structure that functions to keep a resistance value of the electric resistance element constant.

Abstract: A monolithic semiconductor device includes: a substrate; a first nitride semiconductor layer disposed on the substrate; a second nitride semiconductor layer disposed on the first nitride semiconductor layer and having a band gap larger than a band gap of the first nitride semiconductor layer; a first transistor disposed on the substrate and including the first nitride semiconductor layer and the second nitride semiconductor layer, the first transistor being of a high-electron-mobility transistor (HEMT) type for power amplification; and a first bias circuit disposed on the substrate and including a second transistor of the HEMT type disposed outside a propagation path of a radio-frequency signal inputted to the first transistor, the first bias circuit applying bias voltage to a gate of the first transistor.

Abstract: A high-frequency transistor includes a source electrode, a drain electrode, a gate electrode, and a gate drive line that applies a voltage to the gate electrode. An impedance adjustment circuit is connected between the gate electrode and the gate drive line. A characteristic impedance of the gate electrode is Z1, when a connecting point between the impedance adjustment circuit and the gate electrode is viewed from the impedance adjustment circuit. A characteristic impedance of the gate drive line is Z2, when a connecting point between the impedance adjustment circuit and the gate drive line is viewed from the impedance adjustment circuit. X that denotes a characteristic impedance of the impedance adjustment circuit is a value between Z1 and Z2.

Abstract: A resistive element that includes: a substrate; a first nitride semiconductor layer; a second nitride semiconductor layer; a two-dimensional electron gas layer on the first nitride semiconductor layer side at an interface between the first nitride semiconductor layer and the second nitride semiconductor layer; a first electrode ohmically connected to the two-dimensional electron gas layer; a second electrode ohmically connected to the two-dimensional electron gas layer; and an insulating layer between the first electrode and the second electrode in plan view. The two-dimensional electron gas layer functions as an electric resistance element. A conductive layer is not provided above the insulating layer between the first electrode and the second electrode in the plan view. The resistive element has a resistance-value stabilization structure that functions to keep a resistance value of the electric resistance element constant.

Abstract: A high-frequency transistor includes a source electrode, a drain electrode, a gate electrode, and a gate drive line that applies a voltage to the gate electrode. An impedance adjustment circuit is connected between the gate electrode and the gate drive line. A characteristic impedance of the gate electrode is Z1, when a connecting point between the impedance adjustment circuit and the gate electrode is viewed from the impedance adjustment circuit. A characteristic impedance of the gate drive line is Z2, when a connecting point between the impedance adjustment circuit and the gate drive line is viewed from the impedance adjustment circuit. X that denotes a characteristic impedance of the impedance adjustment circuit is a value between Z1 and Z2.

Abstract: A high-frequency transistor includes a source electrode, a drain electrode, a gate electrode, and a gate drive line that applies a voltage to the gate electrode. An impedance adjustment circuit is connected between the gate electrode and the gate drive line. A characteristic impedance of the gate electrode is Z1, when a connecting point between the impedance adjustment circuit and the gate electrode is viewed from the impedance adjustment circuit. A characteristic impedance of the gate drive line is Z2, when a connecting point between the impedance adjustment circuit and the gate drive line is viewed from the impedance adjustment circuit. X that denotes a characteristic impedance of the impedance adjustment circuit is a value between Z1 and Z2.

Abstract: A high-frequency transistor includes a source electrode, a drain electrode, a gate electrode, and a gate drive line that applies a voltage to the gate electrode. An impedance adjustment circuit is connected between the gate electrode and the gate drive line. A characteristic impedance of the gate electrode is Z1, when a connecting point between the impedance adjustment circuit and the gate electrode is viewed from the impedance adjustment circuit. A characteristic impedance of the gate drive line is Z2, when a connecting point between the impedance adjustment circuit and the gate drive line is viewed from the impedance adjustment circuit. X that denotes a characteristic impedance of the impedance adjustment circuit is a value between Z1 and Z2.

Abstract: A bias circuit 12 includes: a transistor Q5 operable to supply, to an amplifier 11, a bias current in accordance with a base current supplied thereto; a transistor Q3 operable to pass a current in accordance with a reference voltage Vref; a transistor Q2 operable to correct, in accordance with the current passed by the transistor Q3, the base current to be supplied to the transistor Q5, so as to compensate a temperature characteristic represented by the transistor Q5; and a bias changing section (of a transistor Q4, and resistances R5, R6, and R7), connected to a base of the transistor Q5, operable to change, in accordance with a control voltage VSW, an amount of the base current to be supplied to the transistor Q5. The amplifier 11 amplifies, by using the bias current supplied by the bias circuit 12, a radio frequency signal having been inputted thereto.

Abstract: Provided are a detector circuit which has a simple circuit configuration, is capable of indicating an accurate power according to a load fluctuation of a radio frequency power amplifier or a difference in a modulation mode, and can be easily incorporated in the radio frequency power amplifier, and a wireless communication system using the detector circuit. The detector circuit 10 includes a detecting resistor 11 for detecting a part of a current flowing from a bias circuit 6, and a current-voltage conversion circuit 12 for converting a current obtained through the detecting resistor 11 into a voltage.

Abstract: Provided are a detector circuit which has a simple circuit configuration, is capable of indicating an accurate power according to a load fluctuation of a radio frequency power amplifier or a difference in a modulation mode, and can be easily incorporated in the radio frequency power amplifier, and a wireless communication system using the detector circuit. The detector circuit 10 includes a detecting resistor 11 for detecting a part of a current flowing from a bias circuit 6, and a current-voltage conversion circuit 12 for converting a current obtained through the detecting resistor 11 into a voltage.

Abstract: To provide a radio frequency power amplifier that realizes a favorable high-frequency characteristic without using an isolator and also achieves low power consumption. The radio frequency power amplifier includes: a power amplifier which amplifies a radio frequency signal; a voltage supplying unit which supplies a collector voltage to the power amplifier; a current supplying unit which supplies a bias current to the power amplifier; and a bias current detecting unit which detects the bias current. The voltage supplying unit has a control unit which sets the power supply voltage at: a first voltage when the detected bias current is lower than a bias-current reference value; and a second voltage lower than the first voltage when the detected bias current is higher than the bias-current reference value.

Abstract: A first FET is inserted in a series position between a signal input terminal and a signal output terminal, while second and third FETs are inserted in a shunt position respectively between the signal input terminal and a ground terminal and between the signal output terminal and a ground terminal. First and second reference voltage terminals and a control terminal are provided. A first reference voltage and a control voltage are applied to the first FET, while a second reference voltage and a control voltage are applied respectively to the second and third FETs, so that the first, second, and third FETs serve as variable resistors. As such, a gain control circuit is constructed. Further, a first resistor is provided in parallel to the first FET, while second and third resistors are provided respectively in series to the second and third FETs.

Abstract: A radio-frequency power amplifier device includes an input terminal for which a first radio-frequency signal for a CDMA mode within a first frequency band and a third radio-frequency signal for a TDMA mode within the first frequency band are selectively provided, a second input terminal for which a second radio-frequency signal for a CDMA mode within a second frequency band and a fourth radio-frequency signal for a TDMA mode within the second frequency band are selectively provided, a first power amplifier unit which to amplifies the provided first radio-frequency signal, a second power amplifier unit which amplifies the provided second radio-frequency signal, a third power amplifier unit which amplifies the provided third radio-frequency signal, and a fourth power amplifier unit which amplifies the provided fourth radio-frequency signal. These power amplifier units are arranged in order of the first power amplifier unit to the fourth power amplifier unit.

Abstract: A bias circuit 12 includes: a transistor Q5 operable to supply, to an amplifier 11, a bias current in accordance with a base current supplied thereto; a transistor Q3 operable to pass a current in accordance with a reference voltage Vref; a transistor Q2 operable to correct, in accordance with the current passed by the transistor Q3, the base current to be supplied to the transistor Q5, so as to compensate a temperature characteristic represented by the transistor Q5; and a bias changing section (of a transistor Q4, and resistances R5, R6, and R7), connected to a base of the transistor Q5, operable to change, in accordance with a control voltage VSW, an amount of the base current to be supplied to the transistor Q5. The amplifier 11 amplifies, by using the bias current supplied by the bias circuit 12, a radio frequency signal having been inputted thereto.

Abstract: Provided are a detector circuit which has a simple circuit configuration, is capable of indicating an accurate power according to a load fluctuation of a radio frequency power amplifier or a difference in a modulation mode, and can be easily incorporated in the radio frequency power amplifier, and a wireless communication system using the detector circuit. The detector circuit 10 includes a detecting resistor 11 for detecting a part of a current flowing from a bias circuit 6, and a current-voltage conversion circuit 12 for converting a current obtained through the detecting resistor 11 into a voltage.

Abstract: A first FET is inserted in a series position between a signal input terminal and a signal output terminal, while second and third FETs are inserted in a shunt position respectively between the signal input terminal and a ground terminal and between the signal output terminal and a ground terminal. First and second reference voltage terminals and a control terminal are provided. A first reference voltage and a control voltage are applied to the first FET, while a second reference voltage and a control voltage are applied respectively to the second and third FETs, so that the first, second, and third FETs serve as variable resistors. As such, a gain control circuit is constructed. Further, a first resistor is provided in parallel to the first FET, while second and third resistors are provided respectively in series to the second and third FETs.