Abstract: A bias circuit 12 includes: a transistor Q5 operable to supply, to an amplifier 11, a bias current in accordance with a base current supplied thereto; a transistor Q3 operable to pass a current in accordance with a reference voltage Vref; a transistor Q2 operable to correct, in accordance with the current passed by the transistor Q3, the base current to be supplied to the transistor Q5, so as to compensate a temperature characteristic represented by the transistor Q5; and a bias changing section (of a transistor Q4, and resistances R5, R6, and R7), connected to a base of the transistor Q5, operable to change, in accordance with a control voltage VSW, an amount of the base current to be supplied to the transistor Q5. The amplifier 11 amplifies, by using the bias current supplied by the bias circuit 12, a radio frequency signal having been inputted thereto.

Abstract: A first FET is inserted in a series position between a signal input terminal and a signal output terminal, while second and third FETs are inserted in a shunt position respectively between the signal input terminal and a ground terminal and between the signal output terminal and a ground terminal. First and second reference voltage terminals and a control terminal are provided. A first reference voltage and a control voltage are applied to the first FET, while a second reference voltage and a control voltage are applied respectively to the second and third FETs, so that the first, second, and third FETs serve as variable resistors. As such, a gain control circuit is constructed. Further, a first resistor is provided in parallel to the first FET, while second and third resistors are provided respectively in series to the second and third FETs.

Abstract: A high frequency part, which amplifies a high frequency signal outputted from an intermediate frequency part and supplies to an antenna, is equipped with a gain controller with switch function. The gain controller with switch function comprises an attenuator with switch function has a function of switching a selected band between two bands outputted from the intermediate frequency part and controlling the gain of the high frequency signal in the selected band. The attenuator with switch function comprises a first variable resistor which connects a signal input part with a signal output part and a second variable resistor which is disposed parallel to said first variable resistor and connects a signal input part with a signal output part. The first and the second variable resistors are controlled by a common gain control voltage and set such that the gain control voltage ranges, which are for changing the resistor values, will not overlap with each other.

Abstract: A bias voltage is applied via a first resistance to the base of a first transistor, and a radio frequency signal is input via a first capacitor to the base of the first transistor. The bias voltage is applied via a second resistance to the base of a second transistor. The bias voltage is applied via a third resistance to the base of a third transistor, and the radio frequency signal RF is input via a third capacitor to the base of the third transistor. A first band rejection filter is provided between the base of the first transistor and the base of the second transistor. A second band rejection filter is provided between the base of the second transistor and the base of the third transistor. The collectors of the first to third transistors are connected in common and the emitters thereof are all grounded.

Abstract: An output level of a transmission apparatus 1 is determined, depending on an attenuation amount of an attenuator 30, a gain of one of a high output level amplification section 17 and a low output level amplification section 18, which is used. A reference voltage Vref(H) is discontinuously changed. Depending on the magnitude of the reference voltage Vref(H), it is determined which of the amplification sections 17, 18 is used, and the attenuation amount of the attenuator 30 and the gain of the amplification section 17, 18 are also determined. When the magnitude of the reference voltage Vref(H) is changed, a sum of the attenuation amount of the attenuator 30 and a gain change amount of a switch amplification section 19 is substantially zero.

Abstract: A gain control circuit 12 comprises an FET 41 operating as a variable resistor. A gate terminal of the FET 41 is supplied with a control voltage VC applied to a gain control terminal 23. A source terminal and a drain terminal of the FET 41 are supplied with a reference voltage Vref1 obtained by a reference voltage circuit 13. The reference voltage Vref1 is controlled so as to compensate for a variation in the threshold voltage of the FET 41. The resistance value of the FET 41 is changed in accordance with the control voltage VC, and thus the gain of the high frequency amplification circuit 10 is also continuously changed.

Abstract: A bias circuit 12 includes: a transistor Q5 operable to supply, to an amplifier 11, a bias current in accordance with a base current supplied thereto; a transistor Q3 operable to pass a current in accordance with a reference voltage Vref; a transistor Q2 operable to correct, in accordance with the current passed by the transistor Q3, the base current to be supplied to the transistor Q5, so as to compensate a temperature characteristic represented by the transistor Q5; and a bias changing section (of a transistor Q4, and resistances R5, R6, and R7), connected to a base of the transistor Q5, operable to change, in accordance with a control voltage VSW, an amount of the base current to be supplied to the transistor Q5. The amplifier 11 amplifies, by using the bias current supplied by the bias circuit 12, a radio frequency signal having been inputted thereto.

Abstract: A bias current to be supplied to an amplification circuit 60 is drawn out of a collector of a transistor Q11 of a bias circuit 10. The drawn-out bias current is input to a base of a transistor Q13 via an attenuation filter F2 and is output from an emitter of the transistor Q13 in the state where the voltage thereof is reduced by a level corresponding to Vbe. The attenuation filter F2 is conducted in a DC manner, and attenuates a component of a frequency fH(=2ft?fr) defined by a transmission frequency ft and a receiving frequency fr of a radio frequency signal. The bias current output from the emitter of the transistor Q13 is supplied to the amplification circuit 60 via an attenuation filter F1. The attenuation filter F1 is conducted in a DC manner, and attenuates a component of a frequency fL(=|fr?ft|).

Abstract: A high frequency part, which amplifies a high frequency signal outputted from an intermediate frequency part and supplies to an antenna, is equipped with a gain controller with switch function. The gain controller with switch function comprises an attenuator with switch function has a function of switching a selected band between two bands outputted from the intermediate frequency part and controlling the gain of the high frequency signal in the selected band. The attenuator with switch function comprises a first variable resistor which connects a signal input part with a signal output part and a second variable resistor which is disposed parallel to said first variable resistor and connects a signal input part with a signal output part. The first and the second variable resistors are controlled by a common gain control voltage and set such that the gain control voltage ranges, which are for changing the resistor values, will not overlap with each other.

Abstract: A transistor integrated circuit apparatus generating less noise, having superb RF characteristics, and preventing thermal runaway of transistors is provided. Owing to capacitors C11 through C1n having one end commonly connected to an RF signal input terminal RFin and the other end connected to a base electrode of a corresponding transistor, and inductors L11 through L1n having one end commonly connected to a DC power supply input terminal DCin and the other end connected to a base electrode of a corresponding transistor, RF noise generated in a DC power supply circuit is reduced. This can reduce the RF noise output from the transistors Tr11 through Tr1n. The inductors L11 through L1n prevent an RF signal input from the RF input terminal RFin from flowing toward the DC power supply circuit. This can prevent the RF signal from being lost by the flow thereof toward the DC power supply circuit.

Abstract: A first FET is inserted in a series position between a signal input terminal and a signal output terminal, while second and third FETs are inserted in a shunt position respectively between the signal input terminal and a ground terminal and between the signal output terminal and a ground terminal. First and second reference voltage terminals and a control terminal are provided. A first reference voltage and a control voltage are applied to the first FET, while a second reference voltage and a control voltage are applied respectively to the second and third FETs, so that the first, second, and third FETs serve as variable resistors. As such, a gain control circuit is constructed. Further, a first resistor is provided in parallel to the first FET, while second and third resistors are provided respectively in series to the second and third FETs.

Abstract: A high frequency part, which amplifies a high frequency signal outputted from an intermediate frequency part and supplies to an antenna, is equipped with a gain controller with switch function. The gain controller with switch function comprises an attenuator with switch function has a function of switching a selected band between two bands outputted from the intermediate frequency part and controlling the gain of the high frequency signal in the selected band. The attenuator with switch function comprises a first variable resistor which connects a signal input part with a signal output part and a second variable resistor which is disposed parallel to said first variable resistor and connects a signal input part with a signal output part. The first and the second variable resistors are controlled by a common gain control voltage and set such that the gain control voltage ranges, which are for changing the resistor values, will not overlap with each other.

Abstract: Provided are: at least one or more series variable resistors implemented by field effect transistors connected to a signal line A; and at least one or more shunt variable resistors implemented by field effect transistors connected between a signal outputting section A and a reference potential section GND. Further provided are: at least one or more series variable resistors implemented by field effect transistors connected to a signal line B arranged in parallel to the signal line A; and at least one or more shunt variable resistors implemented by field effect transistors connected between a signal outputting section B and a reference potential section GND.

Abstract: A first FET is inserted in a series position between a signal input terminal and a signal output terminal, while second and third FETs are inserted in a shunt position respectively between the signal input terminal and a ground terminal and between the signal output terminal and a ground terminal. First and second reference voltage terminals and a control terminal are provided. A first reference voltage and a control voltage are applied to the first FET, while a second reference voltage and a control voltage are applied respectively to the second and third FETs, so that the first, second, and third FETs serve as variable resistors. As such, a gain control circuit is constructed. Further, a first resistor is provided in parallel to the first FET, while second and third resistors are provided respectively in series to the second and third FETs.

Abstract: A bias voltage is applied via a first resistance to the base of a first transistor, and a radio frequency signal is input via a first capacitor to the base of the first transistor. The bias voltage is applied via a second resistance to the base of a second transistor. The bias voltage is applied via a third resistance to the base of a third transistor, and the radio frequency signal RF is input via a third capacitor to the base of the third transistor. A first band rejection filter is provided between the base of the first transistor and the base of the second transistor. A second band rejection filter is provided between the base of the second transistor and the base of the third transistor. The collectors of the first to third transistors are connected in common and the emitters thereof are all grounded.

Abstract: A bias current to be supplied to an amplification circuit 60 is drawn out of a collector of a transistor Q11 of a bias circuit 10. The drawn-out bias current is input to a base of a transistor Q13 via an attenuation filter F2 and is output from an emitter of the transistor Q13 in the state where the voltage thereof is reduced by a level corresponding to Vbe. The attenuation filter F2 is conducted in a DC manner, and attenuates a component of a frequency fH(=2ft?fr) defined by a transmission frequency ft and a receiving frequency fr of a radio frequency signal. The bias current output from the emitter of the transistor Q13 is supplied to the amplification circuit 60 via an attenuation filter attenuates a component of a frequency fL(=|fr?ft|).

Abstract: A first low noise amplifier (LNA1 111) is provided with a control terminal (1115) for turning of/off the low noise amplifier (LNA1 111). Power terminals of the low noise amplifier (LNA1 111) and a second low noise amplifier (LNA2 112) are commonly connected, and are connected to a power supply (10) via a power supply switch (1114). Ground terminals of the two amplifiers (LNA1 111) and (LNA2 112) are commonly connected, and a constant current source (1 115) is connected between the common terminal and the ground. The amplifiers (LNA1 111) and (LNA2 112) are turned on/off by switching the voltage applied to the control terminal (1115) of the first low noise amplifier (LNA1 111) between a high potential and a low potential. The power supply switch (1114) is turned off during signal transmission. Therefore, an LNA block can be provided by using only one power supply switch (1114), whereby it is possible to reduce the number of devices from that in the prior art, thereby realizing a reduction in the size thereof.

Abstract: An output level of a transmission apparatus 1 is determined, depending on an attenuation amount of an attenuator 30, a gain of one of a high output level amplification section 17 and a low output level amplification section 18, which is used. A reference voltage Vref(H) is discontinuously changed. Depending on the magnitude of the reference voltage Vref(H), it is determined which of the amplification sections 17, 18 is used, and the attenuation amount of the attenuator 30 and the gain of the amplification section 17, 18 are also determined. When the magnitude of the reference voltage Vref(H) is changed, a sum of the attenuation amount of the attenuator 30 and a gain change amount of a switch amplification section 19 is substantially zero.

Abstract: A transistor integrated circuit apparatus generating less noise, having superb RF characteristics, and preventing thermal runaway of transistors is provided. Owing to capacitors C11 through C1n having one end commonly connected to an RF signal input terminal RFin and the other end connected to a base electrode of a corresponding transistor, and inductors L11 through L1n having one end commonly connected to a DC power supply input terminal DCin and the other end connected to a base electrode of a corresponding transistor, RF noise generated in a DC power supply circuit is reduced. This can reduce the RF noise output from the transistors Tr11 through Tr1n. The inductors L11 through L1n prevent an RF signal input from the RF input terminal RFin from flowing toward the DC power supply circuit. This can prevent the RF signal from being lost by the flow thereof toward the DC power supply circuit.

Abstract: A gain control circuit 12 comprises an FET 41 operating as a variable resistor. A gate terminal of the FET 41 is supplied with a control voltage VC applied to a gain control terminal 23. A source terminal and a drain terminal of the FET 41 are supplied with a reference voltage Vref1 obtained by a reference voltage circuit 13. The reference voltage Vref1 is controlled so as to compensate for a variation in the threshold voltage of the FET 41. The resistance value of the FET 41 is changed in accordance with the control voltage VC, and thus the gain of the high frequency amplification circuit 10 is also continuously changed.