Patents by Inventor Kandabara N. Tapily

Kandabara N. Tapily has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11804376
    Abstract: A substrate processing method for area selective deposition includes providing a substrate containing a first film, a second film, and a third film, forming a first blocking layer on the first film, forming a second blocking layer on the second film, where the second blocking layer is different from the first blocking layer, and selectively forming a material film on the third film. In one example, the first film contains a metal film, second film contains a metal-containing liner that surrounds the metal film, and the third film includes a dielectric film that surrounds the metal-containing liner.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: October 31, 2023
    Assignee: Tokyo Electron Limited
    Inventor: Kandabara N. Tapily
  • Patent number: 11658066
    Abstract: A substrate processing method includes providing a substrate containing a first film, a second film, and a third film, forming a first blocking layer on the first film, forming a second blocking layer on the second film, where the second blocking layer is different from the first blocking layer, and selectively forming a material film on the third film by vapor deposition. In one example, the first film, second film, and the third film are selected from the group consisting of a metal film, a metal-containing liner, and a dielectric film.
    Type: Grant
    Filed: May 13, 2021
    Date of Patent: May 23, 2023
    Assignee: Tokyo Electron Limited
    Inventor: Kandabara N Tapily
  • Publication number: 20220310812
    Abstract: A semiconductor device includes a first raised feature in a NFET region on a substrate, a first n-type doped epitaxial semiconductor material grown on the first raised feature, the first n-type doped epitaxial material having a first upward facing surface and a first downward facing surface, a first contact metal on the first downward facing surface, and a second contact metal on the first upward facing surface. The device further includes a second raised feature in a PFET region on the substrate, a second p-type doped epitaxial semiconductor material grown on the second raised feature, the second p-type doped epitaxial material having a second upward facing surface and a second downward facing surface, a third contact metal on the second downward facing surface, and a fourth contact metal on the second upward facing surface, wherein the fourth contact metal is different from the second contact metal.
    Type: Application
    Filed: June 15, 2022
    Publication date: September 29, 2022
    Inventors: Hiroaki Niimi, Kandabara N Tapily, Takahiro Hakamata
  • Publication number: 20220310385
    Abstract: Method for gas phase atomic layer deposition (ALD) of aluminum oxide films on patterned substrates using a waterless oxidizer that includes an aluminum alkoxide gas. The method includes providing a substrate containing a dielectric layer and a metal layer or a semiconductor layer, and selectively depositing an aluminum oxide film on a surface of the dielectric layer relative to a surface of the metal layer or a surface of the semiconductor layer by a) exposing the substrate to an aluminum alkyl gas, an aluminum halide gas, or an aluminum hydride gas, and b) exposing the substrate to an aluminum alkoxide gas, where the aluminum alkoxide gas is the principal source of oxygen in the aluminum oxide film.
    Type: Application
    Filed: March 18, 2022
    Publication date: September 29, 2022
    Inventor: Kandabara N. Tapily
  • Patent number: 11443949
    Abstract: A substrate processing method includes providing a substrate containing a first semiconductor material and a second semiconductor material, treating the first semiconductor material and the second semiconductor material with a chemical source that selectively forms a chemical layer on the second semiconductor material relative to the first semiconductor material, and exposing the substrate to a first metal-containing precursor that selectively deposits a first metal-containing layer on the first semiconductor material relative to the chemical layer on the second semiconductor material.
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: September 13, 2022
    Assignee: Tokyo Electron Limited
    Inventor: Kandabara N. Tapily
  • Patent number: 11443953
    Abstract: A processing method includes receiving a substrate containing a base layer having a mandrel pattern formed thereon containing a number of features, conformally depositing a silicon oxide film over the mandrel pattern by coating surfaces of the substrate with a metal-containing catalyst layer, and in the absence of any oxidizing and hydrolyzing agent, exposing the substrate to a process gas containing a silanol gas at a substrate temperature selected to yield a preferred level of stress in the silicon oxide film. The method further includes removing the silicon oxide film from upper surfaces of the mandrel pattern and lower surfaces adjacent the mandrel pattern to leave behind silicon oxide sidewall spacers on sidewalls of the mandrel pattern, and removing the mandrel pattern from the substrate to leave behind the silicon oxide sidewall spacers that form a new pattern having double the number of features of the removed mandrel pattern.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: September 13, 2022
    Assignee: Tokyo Electron Limited
    Inventors: Kandabara N. Tapily, Anton deVilliers, Gerrit J. Leusink
  • Patent number: 11444082
    Abstract: Aspects of the disclosure provide a method for forming a semiconductor apparatus. The method includes forming a first field-effect transistor (FET) that includes a first gate on a substrate of the semiconductor apparatus. The method includes forming a second FET that is stacked on the first FET along a direction substantially perpendicular to the substrate and includes a second gate. The method includes forming a first routing track and a second routing track that is electrically isolated from the first routing track. Each of the first and second routing tracks is provided on a routing plane stacked on the second FET along the direction. A first conductive trace configured to conductively couple the first gate of the first FET to the first routing track can be formed. A second conductive trace configured to conductively couple the second gate of the second FET to the second routing track can be formed.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: September 13, 2022
    Assignee: Tokyo Electron Limited
    Inventors: Jeffrey Smith, Anton J. deVilliers, Kandabara N. Tapily, Subhadeep Kal, Gerrit J. Leusink
  • Patent number: 11374101
    Abstract: A semiconductor device includes a first raised feature in a NFET region on a substrate, a first n-type doped epitaxial semiconductor material grown on the first raised feature, the first n-type doped epitaxial material having a first upward facing surface and a first downward facing surface, a first contact metal on the first downward facing surface, and a second contact metal on the first upward facing surface. The device further includes a second raised feature in a PFET region on the substrate, a second p-type doped epitaxial semiconductor material grown on the second raised feature, the second p-type doped epitaxial material having a second upward facing surface and a second downward facing surface, a third contact metal on the second downward facing surface, and a fourth contact metal on the second upward facing surface, wherein the fourth contact metal is different from the second contact metal.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: June 28, 2022
    Assignee: Tokyo Electron Limited
    Inventors: Hiroaki Niimi, Kandabara N Tapily, Takahiro Hakamata
  • Publication number: 20220044922
    Abstract: Dielectric films for semiconductor devices and methods of forming. A processing method includes forming a first film of a first dielectric material on a substrate by performing a first plurality of cycles of atomic layer deposition and, thereafter, heat-treating the first film, where a thickness of the first film is below a threshold thickness needed for spontaneous polarization in the first dielectric material. The processing method further includes forming a second film of a second dielectric material on the substrate by performing a second plurality of cycles of atomic layer deposition and, thereafter, heat-treating the second film, where a thickness of the second film is greater than the thickness of the first film, and the second film is ferroelectric or antiferroelectric. The first and second dielectric materials can include at least one metal oxide, for example zirconium oxide, hafnium oxide, or a laminate or mixture thereof.
    Type: Application
    Filed: July 30, 2021
    Publication date: February 10, 2022
    Inventors: Dina H. Triyoso, Robert D. Clark, Steven P. Consiglio, Kandabara N. Tapily
  • Publication number: 20210398846
    Abstract: A substrate processing method for area selective deposition. The method includes providing a substrate containing a metal film, a metal-containing liner, and a dielectric film, exposing the substrate to a plasma-excited cleaning gas containing 1) N2 gas and H2 gas, 2) N2 gas followed by H2 gas, or 3) H2 gas followed by N2 gas, forming a blocking layer on the metal film and on the metal-containing liner, and selectively depositing a material film on the dielectric film.
    Type: Application
    Filed: June 11, 2021
    Publication date: December 23, 2021
    Inventors: Kandabara N. Tapily, Shuji Azumo, Yumiko Kawano, Shinichi Ike
  • Publication number: 20210398849
    Abstract: A substrate processing method includes providing a substrate containing a first film, a second film, and a third film, forming a first blocking layer on the first film, forming a second blocking layer on the second film, where the second blocking layer is different from the first blocking layer, and selectively forming a material film on the third film by vapor deposition. In one example, the first film, second film, and the third film are selected from the group consisting of a metal film, a metal-containing liner, and a dielectric film.
    Type: Application
    Filed: May 13, 2021
    Publication date: December 23, 2021
    Inventor: Kandabara N. Tapily
  • Publication number: 20210202244
    Abstract: A high-throughput manufacturing platform and a method for processing semiconductor substrates using the platform. The platform includes a plurality of process modules that include a first process module configured for performing a blocking layer deposition process, a second process module configured for performing a film deposition process, and a third process module configured for performing an etch process, where the blocking layer deposition process requires a longer processing time for each substrate than the film deposition process and the etch process, and where the first process module is configured for simultaneously processing a greater number of substrates than the second and third process modules. A substrate metrology module is hosted on the platform, the substrate metrology module includes an inspection system operable for measuring data associated with an attribute of a substrate at least one of before or after the substrate is processed in a process module of the platform.
    Type: Application
    Filed: December 22, 2020
    Publication date: July 1, 2021
    Inventor: Kandabara N. Tapily
  • Publication number: 20210028169
    Abstract: Aspects of the disclosure provide a method for forming a semiconductor apparatus. The method includes forming a first field-effect transistor (FET) that includes a first gate on a substrate of the semiconductor apparatus. The method includes forming a second FET that is stacked on the first FET along a direction substantially perpendicular to the substrate and includes a second gate. The method includes forming a first routing track and a second routing track that is electrically isolated from the first routing track. Each of the first and second routing tracks is provided on a routing plane stacked on the second FET along the direction. A first conductive trace configured to conductively couple the first gate of the first FET to the first routing track can be formed. A second conductive trace configured to conductively couple the second gate of the second FET to the second routing track can be formed.
    Type: Application
    Filed: September 30, 2020
    Publication date: January 28, 2021
    Applicant: Tokyo Electron Limited
    Inventors: Jeffrey Smith, Anton J. deVilliers, Kandabara N. TAPILY, Subhadeep KAL, Gerrit J. LEUSINK
  • Publication number: 20210020444
    Abstract: A substrate processing method for area selective deposition includes providing a substrate containing a first film, a second film, and a third film, forming a first blocking layer on the first film, forming a second blocking layer on the second film, where the second blocking layer is different from the first blocking layer, and selectively forming a material film on the third film. In one example, the first film contains a metal film, second film contains a metal-containing liner that surrounds the metal film, and the third film includes a dielectric film that surrounds the metal-containing liner.
    Type: Application
    Filed: July 16, 2020
    Publication date: January 21, 2021
    Inventor: Kandabara N. Tapily
  • Patent number: 10833078
    Abstract: Aspects of the disclosure provide a semiconductor apparatus that comprises a first field-effect transistor (FET) formed on a substrate and comprising a first gate, a second FET stacked on the first FET along a direction substantially perpendicular to the substrate and comprising a second gate. The semiconductor apparatus also comprises a first routing track and a second routing track electrically isolated from the first routing track. Each of the first and second routing tracks is provided on a routing plane stacked on the second FET along said direction. The semiconductor apparatus also comprises a first conductive trace configured to conductively couple the first gate of the first FET to the first routing track, and a second conductive trace configured to conductively couple the second gate of the second FET to the second routing track.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: November 10, 2020
    Assignee: Tokyo Electron Limited
    Inventors: Jeffrey Smith, Anton J. deVilliers, Kandabara N. Tapily, Subhadeep Kal, Gerrit J. Leusink
  • Patent number: 10790149
    Abstract: A method of forming crystallographically stabilized ferroelectric hafnium zirconium based films for semiconductor devices is described. The hafnium zirconium based films can be either doped or undoped. The method includes depositing a hafnium zirconium based film with a thickness greater than 5 nanometers on a substrate, depositing a cap layer on the hafnium zirconium based film, heat-treating the substrate to crystallize the hafnium zirconium based film in a non-centrosymmetric orthorhombic phase, a tetragonal phase, or a mixture thereof. The method further includes removing the cap layer from the substrate, thinning the heat-treated hafnium zirconium based film to a thickness of less than 5 nanometers, where the thinned heat-treated hafnium zirconium based film maintains the crystallized non-centrosymmetric orthorhombic phase, the tetragonal phase, or the mixture thereof.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: September 29, 2020
    Assignee: Tokyo Electron Limited
    Inventors: Robert D. Clark, Kandabara N. Tapily
  • Patent number: 10790156
    Abstract: Embodiments of the invention provide a method for atomic layer etching (ALE) of a substrate. According to one embodiment, the method includes providing a substrate, and exposing the substrate to hydrogen fluoride (HF) gas and a boron-containing gas to etch the substrate. According to another embodiment, the method includes providing a substrate containing a metal oxide film, exposing the substrate to HF gas to form a fluorinated surface layer on the metal oxide film, and exposing the substrate to a boron-containing gas to remove the fluorinated surface layer from the metal oxide film. The exposures may be repeated at least once to further etch the metal oxide film.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: September 29, 2020
    Assignee: Tokyo Electron Limited
    Inventors: Robert D. Clark, Kandabara N. Tapily
  • Publication number: 20200303195
    Abstract: A substrate processing method includes providing a substrate containing a first semiconductor material and a second semiconductor material, treating the first semiconductor material and the second semiconductor material with a chemical source that selectively forms a chemical layer on the second semiconductor material relative to the first semiconductor material, and exposing the substrate to a first metal-containing precursor that selectively deposits a first metal-containing layer on the first semiconductor material relative to the chemical layer on the second semiconductor material.
    Type: Application
    Filed: March 18, 2020
    Publication date: September 24, 2020
    Inventor: Kandabara N. Tapily
  • Publication number: 20200279942
    Abstract: A semiconductor device includes a first raised feature in a NFET region on a substrate, a first n-type doped epitaxial semiconductor material grown on the first raised feature, the first n-type doped epitaxial material having a first upward facing surface and a first downward facing surface, a first contact metal on the first downward facing surface, and a second contact metal on the first upward facing surface. The device further includes a second raised feature in a PFET region on the substrate, a second p-type doped epitaxial semiconductor material grown on the second raised feature, the second p-type doped epitaxial material having a second upward facing surface and a second downward facing surface, a third contact metal on the second downward facing surface, and a fourth contact metal on the second upward facing surface, wherein the fourth contact metal is different from the second contact metal.
    Type: Application
    Filed: February 27, 2020
    Publication date: September 3, 2020
    Inventors: Hiroaki Niimi, Kandabara N. Tapily, Takahiro Hakamata
  • Publication number: 20200152473
    Abstract: A processing method includes receiving a substrate containing a base layer having a mandrel pattern formed thereon containing a number of features, conformally depositing a silicon oxide film over the mandrel pattern by coating surfaces of the substrate with a metal-containing catalyst layer, and in the absence of any oxidizing and hydrolyzing agent, exposing the substrate to a process gas containing a silanol gas at a substrate temperature selected to yield a preferred level of stress in the silicon oxide film. The method further includes removing the silicon oxide film from upper surfaces of the mandrel pattern and lower surfaces adjacent the mandrel pattern to leave behind silicon oxide sidewall spacers on sidewalls of the mandrel pattern, and removing the mandrel pattern from the substrate to leave behind the silicon oxide sidewall spacers that form a new pattern having double the number of features of the removed mandrel pattern.
    Type: Application
    Filed: November 13, 2019
    Publication date: May 14, 2020
    Inventors: Kandabara N. Tapily, Anton deVilliers, Gerrit J. Leusink