Patents by Inventor KANG-BIN LEE
KANG-BIN LEE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240125365Abstract: A pad liner includes a first pad clip that surrounds and is coupled to a side protrusion protruding in a lateral direction from a brake pad, and a torque support located under the first pad clip and between a side surface of the brake pad and the caliper body. The torque support supports a braking torque. The first pad clip includes a reference surface located on one of a top surface and a bottom surface of the side protrusion, a vertical elastic portion located on an opposite side from the reference surface that pressurizes the side protrusion in a direction of the reference surface, and a clip side portion that connects the reference surface and the vertical elastic portion and surrounds a side surface of the side protrusion. The pad liner minimizes a vertical gap and movement of the brake pad.Type: ApplicationFiled: October 16, 2023Publication date: April 18, 2024Applicant: HYUNDAI MOBIS CO., LTD.Inventors: Kang Kuk LEE, Seong Hwan AHN, Wan Kyu LEE, In Ho LEE, Yeong Bin CHO
-
Publication number: 20240115545Abstract: The present invention relates to a pharmaceutical composition containing ?-lapachone as an active ingredient for prevention or treatment of cholestatic liver disease, and can provide agents for effectively preventing and treating cholestatic liver disease.Type: ApplicationFiled: October 6, 2021Publication date: April 11, 2024Applicant: CUROME BIOSCIENCES CO., LTD.Inventors: Joo Seog YOON, Kang Sik SEO, Jeong Su HAN, Sung Je MOON, Jung Hoon LEE, Soo Bin YOON
-
Publication number: 20240103663Abstract: A display device includes a display panel including a plurality of touch electrodes, a touch driving circuit electrically connected to the plurality of touch electrodes, and a fingerprint sensor device disposed on one surface of the display panel and including a plurality of unit blocks. The fingerprint sensor device includes a plurality of fingerprint scan lines extending in a first direction, a plurality of fingerprint sensing lines extending in a second direction crossing the first direction, a plurality of sensor pixels respectively connected to the plurality of fingerprint scan lines and the plurality of fingerprint sensing lines, and a fingerprint scan driver having a plurality of stages for applying a fingerprint scan signal to each of the plurality of fingerprint scan lines. The touch driving circuit applies a start signal to the fingerprint scan driver.Type: ApplicationFiled: November 27, 2023Publication date: March 28, 2024Inventors: Kyung Tea PARK, Hyun Dae LEE, Kang Bin JO, Jong Hyun LEE
-
Patent number: 11929032Abstract: A display device comprises a display panel which comprises scan lines, sensing lines, pixels electrically connected to each of the scan lines, and photo sensors electrically to each of the scan lines and the sensing lines, a scan driver which outputs scan signals to the scan lines according to a scan control signal, a timing controller which outputs the scan control signal to the scan driver, and a readout circuit which receives light sensing signals of the photo sensors from the sensing lines. The timing controller sets a frame frequency of the scan control signal to a first frame frequency in a first mode in which the display panel displays an image. The timing controller sets the frame frequency of the scan control signal to a second frame frequency in a second mode in which the photo sensors sense a fingerprint.Type: GrantFiled: August 15, 2022Date of Patent: March 12, 2024Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Hyun Dae Lee, Il Nam Kim, Seung Hyun Moon, Dong Wook Yang, Kang Bin Jo, Go Eun Cha
-
Publication number: 20240078835Abstract: An input sensing device includes: sensor pixels, a horizontal driver, a selection circuit, and a vertical driver. Each of the sensor pixels is connected to a plurality of driving lines and a one of a plurality of signal input lines. The horizontal driver sequentially applies a horizontal driving signal to the sensor pixels through the driving lines. The selection circuit is connected to n of the signal input lines (n is a natural number of 2 or more) and to one output line. The selection circuit sequentially outputs n sensing signals received through the n signal input lines to the one output line. The vertical driver receives the n sensing signals through the one output line. The horizontal driver applies the horizontal driving signal n times to a given one of the driving lines to correspond to the n sensing signals.Type: ApplicationFiled: November 8, 2023Publication date: March 7, 2024Inventors: Kyung Tea PARK, Jong Hyun LEE, Kang Bin JO, Go Eun CHA
-
Publication number: 20240078836Abstract: An input sensing device includes: sensor pixels, a horizontal driver, a selection circuit, and a vertical driver. Each of the sensor pixels is connected to a plurality of driving lines and a one of a plurality of signal input lines. The horizontal driver sequentially applies a horizontal driving signal to the sensor pixels through the driving lines. The selection circuit is connected to n of the signal input lines (n is a natural number of 2 or more) and to one output line. The selection circuit sequentially outputs n sensing signals received through the n signal input lines to the one output line. The vertical driver receives the n sensing signals through the one output line. The horizontal driver applies the horizontal driving signal n times to a given one of the driving lines to correspond to the n sensing signals.Type: ApplicationFiled: November 8, 2023Publication date: March 7, 2024Inventors: Kyung Tea PARK, Jong Hyun LEE, Kang Bin JO, Go Eun CHA
-
Patent number: 11798629Abstract: Each of memory blocks of a nonvolatile memory device includes a memory cell region including first metal pads, first memory cells of a first portion of pillar, and second memory cells of a second portion of the pillar, and a peripheral circuit region including second metal pads, a row decoder, and a page buffer. When performing program operations based on consecutive addresses at a memory block selected from the memory blocks, the nonvolatile memory device sequentially completes first program operations of non-adjacent memory cells not adjacent to a boundary of the first portion and the second portion from among the first and second memory cells and then completes a second program operation of an adjacent memory cell adjacent to the boundary. The peripheral circuit region is vertically connected to the memory cell region by the first metal pads and the second metal pads directly.Type: GrantFiled: September 30, 2021Date of Patent: October 24, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yonghyuk Choi, Jae-Duk Yu, Kang-Bin Lee, Sang-Won Shim, Bongsoon Lim
-
Publication number: 20230197161Abstract: A memory device includes a memory cell region including a first metal pad, a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first and second metal pads, a memory cell array in the memory cell region including cell strings including memory cells, word lines respectively connected to the memory cells, bit lines connected to one side of the cell strings, and a ground selection line connected to the cell strings, a control logic in the peripheral circuit region including a precharge control circuit for controlling precharge on partial cell strings among the cell strings and controlling a plurality of data program steps on the memory cells, and a row decoder in the peripheral circuit region for activating at least some of the word lines in response to a control of the control logic.Type: ApplicationFiled: February 23, 2023Publication date: June 22, 2023Inventors: SUNG-MIN JOE, Kang-Bin LEE
-
Patent number: 11600331Abstract: A memory device includes a memory cell region including a first metal pad, a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first and second metal pads, a memory cell array in the memory cell region including cell strings including memory cells, word lines respectively connected to the memory cells, bit lines connected to one side of the cell strings, and a ground selection line connected to the cell strings, a control logic in the peripheral circuit region including a precharge control circuit for controlling precharge on partial cell strings among the cell strings and controlling a plurality of data program steps on the memory cells, and a row decoder in the peripheral circuit region for activating at least some of the word lines in response to a control of the control logic.Type: GrantFiled: November 11, 2021Date of Patent: March 7, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung-Min Joe, Kang-Bin Lee
-
Publication number: 20220068394Abstract: A memory device includes a memory cell region including a first metal pad, a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first and second metal pads, a memory cell array in the memory cell region including cell strings including memory cells, word lines respectively connected to the memory cells, bit lines connected to one side of the cell strings, and a ground selection line connected to the cell strings, a control logic in the peripheral circuit region including a precharge control circuit for controlling precharge on partial cell strings among the cell strings and controlling a plurality of data program steps on the memory cells, and a row decoder in the peripheral circuit region for activating at least some of the word lines in response to a control of the control logic.Type: ApplicationFiled: November 11, 2021Publication date: March 3, 2022Inventors: SUNG-MIN JOE, KANG-BIN LEE
-
Publication number: 20220020434Abstract: Each of memory blocks of a nonvolatile memory device includes a memory cell region including first metal pads, first memory cells of a first portion of pillar, and second memory cells of a second portion of the pillar, and a peripheral circuit region including second metal pads, a row decoder, and a page buffer. When performing program operations based on consecutive addresses at a memory block selected from the memory blocks, the nonvolatile memory device sequentially completes first program operations of non-adjacent memory cells not adjacent to a boundary of the first portion and the second portion from among the first and second memory cells and then completes a second program operation of an adjacent memory cell adjacent to the boundary. The peripheral circuit region is vertically connected to the memory cell region by the first metal pads and the second metal pads directly.Type: ApplicationFiled: September 30, 2021Publication date: January 20, 2022Inventors: YONGHYUK CHOI, JAE-DUK YU, KANG-BIN LEE, SANG-WON SHIM, BONGSOON LIM
-
Patent number: 11217311Abstract: A memory device includes a memory cell region including a first metal pad, a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first and second metal pads, a memory cell array in the memory cell region including cell strings including memory cells, word lines respectively connected to the memory cells, bit lines connected to one side of the cell strings, and a ground selection line connected to the cell strings, a control logic in the peripheral circuit region including a precharge control circuit for controlling precharge on partial cell strings among the cell strings and controlling a plurality of data program steps on the memory cells, and a row decoder in the peripheral circuit region for activating at least some of the word lines in response to a control of the control logic.Type: GrantFiled: July 13, 2020Date of Patent: January 4, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung-Min Joe, Kang-Bin Lee
-
Patent number: 11158379Abstract: Each of memory blocks of a nonvolatile memory device includes a memory cell region including first metal pads, first memory cells of a first portion of pillar, and second memory cells of a second portion of the pillar, and a peripheral circuit region including second metal pads, a row decoder, and a page buffer. When performing program operations based on consecutive addresses at a memory block selected from the memory blocks, the nonvolatile memory device sequentially completes first program operations of non-adjacent memory cells not adjacent to a boundary of the first portion and the second portion from among the first and second memory cells and then completes a second program operation of an adjacent memory cell adjacent to the boundary. The peripheral circuit region is vertically connected to the memory cell region by the first metal pads and the second metal pads directly.Type: GrantFiled: July 22, 2020Date of Patent: October 26, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yonghyuk Choi, Jae-Duk Yu, Kang-Bin Lee, Sang-Won Shim, Bongsoon Lim
-
Patent number: 11152074Abstract: A memory device includes a memory cell region including a first metal pad, a peripheral circuit region including a second metal pad and connected to the memory cell region by the first and second metal pads, and a memory cell array in the memory cell region and including cell strings. The cell strings include memory cells, word lines and dummy lines connected to the memory cells, bit lines connected to one side of the cell strings, and a ground selection line connected to the cell strings. The memory device further includes control logic in the peripheral circuit region and including a precharge control circuit that controls a precharge on partial cell strings among the cell strings and controls data program steps on the memory cells, and a row decoder in the peripheral circuit region that activates at least some of the word lines based on control of the control logic.Type: GrantFiled: August 20, 2020Date of Patent: October 19, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung-Min Joe, Kang-Bin Lee
-
Patent number: 11043274Abstract: Each of memory blocks of a nonvolatile memory device includes first memory cells of a first portion of pillar and second memory cells of a second portion of the pillar. When performing program operations based on consecutive addresses at a memory block selected from the memory blocks, the nonvolatile memory device sequentially completes first program operations of non-adjacent memory cells not adjacent to a boundary of the first portion and the second portion from among the first and second memory cells and then completes a second program operation of an adjacent memory cell adjacent to the boundary.Type: GrantFiled: April 17, 2020Date of Patent: June 22, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yonghyuk Choi, Jae-Duk Yu, Kang-Bin Lee, Sang-Won Shim, Bongsoon Lim
-
Publication number: 20210065806Abstract: Each of memory blocks of a nonvolatile memory device includes a memory cell region including first metal pads, first memory cells of a first portion of pillar, and second memory cells of a second portion of the pillar, and a peripheral circuit region including second metal pads, a row decoder, and a page buffer. When performing program operations based on consecutive addresses at a memory block selected from the memory blocks, the nonvolatile memory device sequentially completes first program operations of non-adjacent memory cells not adjacent to a boundary of the first portion and the second portion from among the first and second memory cells and then completes a second program operation of an adjacent memory cell adjacent to the boundary. The peripheral circuit region is vertically connected to the memory cell region by the first metal pads and the second metal pads directly.Type: ApplicationFiled: July 22, 2020Publication date: March 4, 2021Inventors: Yonghyuk Choi, Jae-Duk Yu, Kang-Bin Lee, Sang-Won Shim, Bongsoon Lim
-
Publication number: 20210065805Abstract: Each of memory blocks of a nonvolatile memory device includes first memory cells of a first portion of pillar and second memory cells of a second portion of the pillar. When performing program operations based on consecutive addresses at a memory block selected from the memory blocks, the nonvolatile memory device sequentially completes first program operations of non-adjacent memory cells not adjacent to a boundary of the first portion and the second portion from among the first and second memory cells and then completes a second program operation of an adjacent memory cell adjacent to the boundary.Type: ApplicationFiled: April 17, 2020Publication date: March 4, 2021Inventors: Yonghyuk CHOI, Jae-Duk Yu, Kang-Bin Lee, Sang-Won Shim, Bongsoon Lim
-
Patent number: 10892015Abstract: In a method of programming in a nonvolatile memory device, channels of a plurality of cell strings are precharged through ground selection transistors by a precharge voltage of a source line. A turn-on voltage is applied to a selected ground selection transistor of a selected cell string among the plurality of cell strings, during a verification read period of an N-th program loop. The turn-on voltage applied to the selected ground selection transistor is maintained to precharge the channels for an (N+1)-th program loop, without recovery after the verification read period of the N-th program loop is finished. Power consumption is reduced and an operation speed is increased by maintaining the turn-on voltage of the selected ground selection line to precharge the channels of the cell strings without recovery after the verification read operation is finished.Type: GrantFiled: March 18, 2020Date of Patent: January 12, 2021Inventors: Kang-Bin Lee, Il-Han Park, Jong-Hoo Jo
-
Publication number: 20200381065Abstract: A memory device includes a memory cell region including a first metal pad, a peripheral circuit region including a second metal pad and connected to the memory cell region by the first and second metal pads, and a memory cell array in the memory cell region and including cell strings. The cell strings include memory cells, word lines and dummy lines connected to the memory cells, bit lines connected to one side of the cell strings, and a ground selection line connected to the cell strings. The memory device further includes control logic in the peripheral circuit region and including a precharge control circuit that controls a precharge on partial cell strings among the cell strings and controls data program steps on the memory cells, and a row decoder in the peripheral circuit region that activates at least some of the word lines based on control of the control logic.Type: ApplicationFiled: August 20, 2020Publication date: December 3, 2020Inventors: SUNG-MIN JOE, Kang-Bin Lee
-
Patent number: 10854250Abstract: A memory device comprises a memory cell array including a first memory cell disposed on a substrate and a second memory cell above the first memory cell; a first word line connected to the first memory cell and a second word line connected to the second memory cell, the second word line disposed above the first word line; and a word line defect detection circuit configured to monitor a number of pulses of a pumping clock signal while applying a first voltage to the first word line to detect a defect of the first word line. The voltage generator is configured to apply a second voltage different from the first voltage to the second word line for programming the second memory cell when the number of pulses of the pumping clock signal is smaller than a reference value.Type: GrantFiled: June 5, 2018Date of Patent: December 1, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae-Yun Lee, Joon Soo Kwon, Byung Soo Kim, Su-Yong Kim, Sang-Soo Park, Il Han Park, Kang-Bin Lee, Jong-Hoon Lee, Na-Young Choi