Patents by Inventor Kanji Otsuka

Kanji Otsuka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5304844
    Abstract: A semiconductor device is provided having a semiconductor pellet that is arranged on a substantially central part of a film base in which a metal plate is overlaid with an insulating member, while inner leads are arranged on a peripheral part of the film base in a state in which they are electrically isolated from the metal plate of the film base. External terminals for a power source among external terminals of the semiconductor pellet and middle parts of the metal plate of the film base, as well as inner leads for the power source among the inner leads and peripheral parts of the metal plate are electrically connected by pieces of bonding wire, respectively.
    Type: Grant
    Filed: May 28, 1992
    Date of Patent: April 19, 1994
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Osamu Horiuchi, Gen Murakami, Hiromichi Suzuki, Hajime Hasebe, Kanji Otsuka, Yuuji Shirai, Takayuki Okinaga, Takashi Emata
  • Patent number: 5258649
    Abstract: A silicon chip is mounted on a portion a heat dissipation body, and a carrier film is inserted into a resin composition material. Each of input/output electrode portions of the silicon chip is connected electrically to each of lead wires of the carrier film. The electrical connection between the silicon chip and a circuit substrate is carried out by the carrier film. Another portion of the heat dissipation body is exposed on a surface of the resin composition material. A fixing means for fixing the resin composition material is formed integrally to the resin composition material or to the heat dissipation body. The resin composition material is fixed to a circuit substrate through the fixing means. The mechanical fixing between the resin composition material and the circuit substrate is carried out by the fixing means, which is separate from the carrier film. A heat dissipation fin may be provided on the heat dissipation body.
    Type: Grant
    Filed: July 23, 1992
    Date of Patent: November 2, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Akira Tanaka, Kazuji Yamada, Tadahiko Miyoshi, Kanji Otsuka
  • Patent number: 5234866
    Abstract: According to the present invention, as improvement in the adhesion of inner leads with a packaging resin in a resin-sealed semiconductor device is attained by spreading leads on or near the circuit-forming face of a pellet, or on or near the main non-circuit-forming face of the pellet to extend the lengths of the inner leads on or under the pellet.
    Type: Grant
    Filed: April 3, 1992
    Date of Patent: August 10, 1993
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Takayuki Okinaga, Hiroshi Tachi, Hiroshi Ozaki, Kanji Otsuka, Michiaki Furukawa, Yasuyuki Yamasaki
  • Patent number: 5217922
    Abstract: A method of manufacturing a semiconductor device wherein the back surface of a semiconductor chip is adhered closely to a substrate or a seal member through a soldering material or the like, and a metallized layer is formed on the back surface of the chip for attaining good adhesion. The metallized layer according to the present invention is a layer formed by laminating a metal silicide, a barrier metal and an oxidation preventing metal successively on the back of the chip. The layer of the metal silicide can be formed in a known heat treatment process, for example, simultaneously with the formation of bump electrodes, on a main surface of the semiconductor chip by the heat used at the time of forming such bump electrodes, or simultaneously with the mounting of the semiconductor chip by the heat used at the time of the chip mounting.
    Type: Grant
    Filed: December 19, 1991
    Date of Patent: June 8, 1993
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Hiroshi Akasaki, Kanji Otsuka, Tetsuya Hayashida
  • Patent number: 5195576
    Abstract: An LSI cooling apparatus having various structures is used in electronic devices such as computer systems. In particular, the LSI cooling of apparatus is suitable for cooling of LSIs having high heat generating densities. In a cooling apparatus of the present invention, a heat sink is constructed to be small in pressure loss and excellent in cooling performance. This is because the heat sink comprises thin wire fins so set that the Reynold's number may not exceed 40. As a result, LSIs generating a large amount of heat can be cooled. Further, a heat sink having rigidity can be obtained by disposing wide-width wire drawn substances in thin wires or by using supports. Further, a computer comprising LSIs equipped with heat sinks can cope with various cooling air sending methods and it can be cooled with low noises.
    Type: Grant
    Filed: February 25, 1991
    Date of Patent: March 23, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Toshio Hatada, Hitoshi Matsushima, Yoshihiro Kondou, Hiroshi Inoue, Kanji Otsuka, Yuji Shirai, Takao Ohba, Akira Yamagiwa
  • Patent number: 5191224
    Abstract: To achieve higher packaging density and one wafer level for a full-sized wafer memory, or wafer-scale integration memory system, the wafers are vertically stacked with each other at a predetermined interval. A packaging technique is improved in such a way that a memory system layout can be precisely realized and a precise through hole can be formed. Moreover, other chips are fixed on the wafer so as to achieve furthermore the high packaging density.
    Type: Grant
    Filed: December 13, 1990
    Date of Patent: March 2, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Masanori Tazunoki, Hiromitsu Mishimagi, Makoto Homma, Toshiyuki Sakuta, Hisashi Nakamura, Keiji Sasaki, Minoru Enomoto, Toshihiko Satoh, Kunizo Sahara, Shigeo Kuroda, Kanji Otsuka, Masao Kawamura, Hinoko Kurosawa, Kazuya Ito
  • Patent number: 5188280
    Abstract: A technique for producing a chip mount type package or a TAB package with high reliability, without use of a flux which would cause environmental pollution or would hinder an enhancement of reliability, more particularly pertains to a method of irradiating bonding surfaces, for which a solder is used, and solder bump electrodes of a package with an atomic or ion energy beam, and bonding the bonding surfaces to each other under normal pressure (about 1 atm) in a continuous apparatus.
    Type: Grant
    Filed: December 23, 1991
    Date of Patent: February 23, 1993
    Assignees: Hitachi Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Takashi Nakao, Yoshiaki Emoto, Koichiro Sekiguchi, Masayuki Iketani, Kunizo Sahara, Ikuo Yoshida, Akiomi Kohno, Masaya Horino, Hideaki Kamohara, Shouichi Irie, Hiroshi Akasaki, Kanji Otsuka
  • Patent number: 5126821
    Abstract: According to the present invention, as improvement in the adhesion of inner leads with a packaging resin in a resin-sealed semiconductor device is attained by spreading leads on or near the circuit-forming face of a pellet, or on or near the main non-circuit-forming face of the pellet to extend the lengths of the inner leads on or under the pellet.
    Type: Grant
    Filed: May 29, 1990
    Date of Patent: June 30, 1992
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Takayuki Okinaga, Hiroshi Tachi, Hiroshi Ozaki, Kanji Otsuka, Michiaki Furukawa, Yasuyuki Yamasaki
  • Patent number: 5107329
    Abstract: A semiconductor device of pin-grid array (PGA) type, which is adapted for surface-mounting on a printed circuit board, has lead pins arranged in a grid and standing perpendicularly on a base of the semiconductor device. In addition, a few pins are provided which are longer than said lead pins in said grid. When the device is placed on the printed circuit board for mounting, the longer pins are inserted into through-holes which are respectively formed in the printed circuit board to correspond to the position of the longer pins of the device. Thus, the tip of the lead pins are accurately positioned on the top of lands on the printed circuit board, respectively, and the lead pins do not get out of position during the mounting operation.
    Type: Grant
    Filed: February 27, 1989
    Date of Patent: April 21, 1992
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Takayuki Okinaga, Kanji Otsuka, Hiroshi Akasaki
  • Patent number: 5090609
    Abstract: An invention relating to a technique for producing a chip mount type package or a TAB package with high reliability, without use of a flux which would cause environmental pollution or would hinder an enhancement of reliability, and more particularly pertaining to a method of irradiating bonding surfaces, for which a solder is used, and solder bump electrodes of a package with an atomic or ion energy beam and bonding the bonding surfaces to each other under normal pressure (about 1 atm) in a continuous apparatus.
    Type: Grant
    Filed: April 26, 1990
    Date of Patent: February 25, 1992
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Takashi Nakao, Yoshiaki Emoto, Koichiro Sekiguchi, Masayuki Iketani, Kunizo Sahara, Ikuo Yoshida, Akiomi Kohno, Masaya Horino, Hideaki Kamohara, Shouichi Irie, Hiroshi Akasaki, Kanji Otsuka
  • Patent number: 5067007
    Abstract: Attempts have been made to increase the number of pins of packages accompanying the trend toward fabricating integrated circuits highly densely and in smaller sizes. The present invention provides technology for improving reliability in fabricating packages of the surface-mounted type that have increased number of pins. That is, when the packages are mounted on the wiring substrate, the lead pins that receive load from the axial direction exhibit bending strength which is smaller than the junction strength of solder at the junction portions. To achieve this object, the lead pins are made of a material having large resiliency such as a fiber-reinforced material, a transformation pseudo elastic material, an ultra-high tension material, or a heat-resistant ultra-high tension material.
    Type: Grant
    Filed: January 24, 1991
    Date of Patent: November 19, 1991
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Kanji Otsuka, Masao Kato, Takashi Kumagai, Mitsuo Usami, Shigeo Kuroda, Kunizo Sahara, Takeo Yamada, Seiji Miyamoto, Yuuji Shirai, Takayuki Okinaga, Kazutoshi Kubo, Hiroshi Tachi, Masayuki Kawashima
  • Patent number: 5053480
    Abstract: A polyimide resin composed essentially of repeating units represented by the general formula: ##STR1## where R is a divalent aromatic hydrocarbon radical.
    Type: Grant
    Filed: April 2, 1990
    Date of Patent: October 1, 1991
    Assignee: Nissan Chemical Industries, Ltd.
    Inventors: Noriaki Koto, Toyohiko Abe, Hideo Suzuki, Kanji Otsuka
  • Patent number: 5032895
    Abstract: A semiconductor device comprising the fact that a semiconductor pellet is arranged on a substantially central part of a film base in which a metal plate is overlaid with an insulating member, while inner leads are arranged on a peripheral part of the film base in a state in which they are electrically isolated from the metal plate of the film base, and that external terminals for a power source among external terminals of the semiconductor pellet and middle parts of the metal plate of the film base, and inner leads for the power source among the inner leads and peripheral parts of the metal plate are electrically connected by pieces of bonding wire, respectively.
    Type: Grant
    Filed: April 18, 1990
    Date of Patent: July 16, 1991
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Osamu Horiuchi, Gen Murakami, Hiromichi Suzuki, Hajime Hasebe, Kanji Otsuka, Yuuji Shirai, Takayuki Okinaga, Takashi Emata
  • Patent number: 5018004
    Abstract: A semiconductor chip package technology which uses thin film wiring from the chip to the package terminals for increased line density and decreased parasitic capacitance and uses a thin film adhesion layer for improved heat conductivity between the package substrate and its sealing cap. The package uses a thin conductor film deposited along the element mounting surface of a sintered substrate. An adhesion layer, to provide a high quality bond between the sealing cap and substrate, is then deposited on the substrate peripheral area by successively laminating metal and metallized layers, or by depositing a single layer of low metal glass. The adhesion layer is thinner and of larger area than thick film technology, for improved heat conduction.
    Type: Grant
    Filed: November 28, 1989
    Date of Patent: May 21, 1991
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Takayuki Okinaga, Shouji Matsugami, Yuuji Shirai, Kanji Otsuka, Hiroshi Koguma, Takashi Emata
  • Patent number: 4965660
    Abstract: An integrated circuit package produced by bonding a rear surface of an insulating substrate enclosed in the package to a heat sink such as a cooling fin by a resinous adhesive, which may include one or more fillers, having a Young's modulus of 500 kg/cm.sup.2 or less when formed into a film, has high reliability at the bonding portion and withstands without damages even if subjected to thermal shocks.
    Type: Grant
    Filed: June 12, 1989
    Date of Patent: October 23, 1990
    Assignee: Hitachi, Ltd.
    Inventors: Satoru Ogihara, Hironori Kodama, Nobuyuki Ushifusa, Kanji Otsuka
  • Patent number: 4965653
    Abstract: The present invention discloses a suitable mounting of a wafer scale LSI (wafer scale integration) (WSI) in which a slit formed in a wafer is fit to a connector, a U-shaped reinforcing rubber member is disposed at the circumferential edge of the wafer, or a flexible adhesive is used for bonding a substrate formed with through-holes and a wafer, to provide a WSI mounting structure of high integration degree and high reliability. Furthermore, a method of efficient mounting by conducting the wiring of the wafer and the connection with the external terminal of the chip in one identical production step is disclosed.
    Type: Grant
    Filed: February 28, 1990
    Date of Patent: October 23, 1990
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Kanji Otsuka, Shigeo Kuroda, Katsuyuki Sato, Hisashi Nakamura, Shinichi Shouji
  • Patent number: 4943843
    Abstract: According to the present invention, as improvement in the adhesion of inner leads with a packaging resin in a resin-sealed semiconductor device is attained by spreading leads on or near the circuit-forming face of a pellet, or on or near the main non-circuit-forming face of the pellet to extend the lengths of the inner leads on or under the pellet.
    Type: Grant
    Filed: December 8, 1989
    Date of Patent: July 24, 1990
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Takayuki Okinaga, Hiroshi Tachi, Hiroshi Ozaki, Kanji Otsuka, Michiaki Furukawa, Yasuyuki Yamasaki
  • Patent number: 4886573
    Abstract: In a process for forming a wiring conductor of Cu, Al, Au or the like on a wiring substrate, polyimide-based resin having the following unit structural formula is used as a lift-off material. ##STR1## wherein R.sub.1 : ##STR2## R.sub.2 : ##STR3## n is an integer of 15,000 to 30,000. This lift-off material has very good etching susceptibility and can be selectively lifted off with an etching solution of a mixture of hydrazine and ethylene diamine from a lower polyimide layer having R.sub.1 : ##STR4## R.sub.2 : ##STR5## .
    Type: Grant
    Filed: August 19, 1987
    Date of Patent: December 12, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Hiroshi Watanabe, Osamu Miura, Kunio Miyazaki, Shunichi Numata, Kanji Otsuka
  • Patent number: 4764804
    Abstract: A semiconductor device having improved heat-dissipating characteristics employs a thin insulator film made of diamond, which has excellent thermal conductivity, as an insulator film which is formed on a chip immediately below a heat-dissipating bump electrode. Since the thin diamond film has excellent insulating properties and high thermal conductivity, it is possible to improve heat-dissipating characteristics of even a high-power semiconductor device such as a multichip module. In the case of, particularly, a multichip module, the insulation between a mother chip and a child chip can also be ensured by the presence of the thin diamond film.
    Type: Grant
    Filed: February 17, 1987
    Date of Patent: August 16, 1988
    Assignee: Hitachi, Ltd.
    Inventors: Kunizo Sahara, Kanji Otsuka, Hisashi Ishida
  • Patent number: 4729010
    Abstract: An integrated circuit package in which semiconductor elements mounted on an insulating substrate, ends of lead pieces introduced from the outside and wires that electrically connect them, are accommodated in a cell that is air-tightly defined by the substrate, a cap and a sealing glass. The lead pieces are composed of an alloy having a coefficient of thermal expansion nearly equal to, or smaller than, the coefficient of thermal expansion of the substrate. The alloy is an iron alloy which contains nickel and cobalt, and having a martensite transformation temperture of lower than -55.degree. C.
    Type: Grant
    Filed: July 30, 1986
    Date of Patent: March 1, 1988
    Assignee: Hitachi, Ltd.
    Inventors: Masatoshi Tsuchiya, Satoru Ogihara, Hiromi Kagohara, Kanji Otsuka, Tomoji Oishi