Abstract: A clockless synchronizer (200) is used for sub-rate bit acquisition and synchronization of high speed clockless data streams. Clockless synchronizer (200) comprises burst detector (210), multi-phase signal generator (220), multi-phase signal router (230), multi-phase signal sampler (240), clock generator (250), correlation control circuit (260), and output data selector (270). Clockless synchronizer (200) is fabricated on a single ASIC, and it is free from the ‘data rate less than the available clock’ limitation.

Abstract: A method and apparatus for steering beams modulated from a mobile platform in a manner that reduces overall platform payload processing, and therefore payload weight and power requirements. According to the present invention, a beam steering data calculator (64) generates a table of beam steering data sets (60a, 60b), with each data set corresponding to a specific beam-pointing angle mapped to a corresponding cell on the surface of the earth. A data set that corresponds to a received downlink cell address (22a-22e) is read out from the table and mapped to the downlink address, and an output angle of a modulated vehicle beam (16a-16e) that transmits a data packet to the cell address is corrected to correspond to the beam-pointing angle of the read-out data set.

Abstract: A data processing system (20) schedules the allocation of a common bus (26), used by multiple service requesters (32). The system (20) creates a plurality of service request levels (44) and assigns each service requester (32) to one of the plurality of request levels (44). Services of the common bus (26) are provided to all service requesters (32) assigned to a first service request level (44) for each instance of providing service to one of the service requesters (32) assigned to a second service request level (44). The method then again provides services of the common bus (26) to all service requesters (32) assigned to the first service request level (44) for a single instance of providing service to one of the second level requesters (32).

Abstract: A communication network (10) includes packet switching nodes (18) in which packets from high speed data links (20, 22) are switched onto a multiplicity of low speed data links (26). Each node (18) includes a bulk RAM (30) which has a section (32) dedicated to implementing a multiplicity of logically independent FIFO buffers. A routing controller (46) controls DMA transfers of packets into and out from appropriate FIFO buffers. Packets are transferred into respective FIFO buffers consecutively and transferred out from respective FIFO buffers interleaved together.