Abstract: An embodiment of the invention includes a pair of parallel 16×16 multipliers each with two 32-bit inputs and one 32-bit output. There are options to allow input halfword and byte selection for four independent 8×8 or two independent 16×16 multiplications, real and imaginary parts of comple×multiplication, pairs of partial sums for 32×32 multiplication, and partial sums for 16×32 multiplication. There are options to allow internal hardwired routing of each multiplier unit results to achieve partial-sum shifting as required to support above options. There is a redundant digit arithmetic adder before final outputs to support additions for partial sum accumulation, complex multiplication vector accumulation and general accumulation for FIRs/IIRs—giving MAC unit functionality. There are options controlled using bit fields in a control register passed to the multiplier unit as an operand.

Abstract: A method for processing data using a multiplexing architecture is provided that includes performing a selected one of a plurality of first multiplexer operations on the data such that a first output is produced. The method also includes performing a selected one of a plurality of second multiplexer operations on the first output such that a second output is produced. A result is then generated that reflects the first and second outputs produced by first and second multiplexers respectively.

Abstract: This invention is a data processing apparatus which operates on instruction controlling plural processor actions. Each instruction includes a data unit section and a data transfer section. These instruction sections are independent and may include differing options. In the preferred embodiment, each instruction is 64 bits. The data unit section includes a data operation field that indicates the type of arithmetic logic unit operation and six operand fields. The six operand fields include four source data register fields and two destination register fields. The data unit (110) includes a multiplication unit (220) and an arithmetic logic unit (230). The data unit (110) may include a barrel rotator (235) for one input of the arithmetic logic unit (230). The rotated data may be stored in the first destination register instead of the multiply result. The address unit (120) operations according to the data transfer operation field. This could be a load, a store or a register to register move.

Abstract: A data processing apparatus including a multiplier unit forming a product from L bits of each two data buses of N bits each N is greater than L. The multiplier forms a N bit output having a first portion which is the L most significant bits of the of product and a second portion which is M other bits not including the L least significant bits of the product, where N is the sum of M and L. In the preferred embodiment the M other bits are derived from other bits of the two input data busses, such as the M other bits of the first input data bus. An arithmetic logic unit performs parallel operations (addition, subtraction, Boolean functions) controlled by the same instructions. This arithmetic logic unit is divisible into a selected number of sections for performing identical operations on independent sections of its inputs. The multiplier unit may form dual products from separate parts of the input data.

Abstract: Data transfer between multiple processor nodes and multiple static memory storage nodes is made more efficient using a wrapper of logic surrounding a conventional single port static memory function. The wrapper logic comprises FIFO devices which provide buffering between a given processor node and its associated memory function. The added buffering allows the design to trade allowable added read and write latency for a significant reduction in memory complexity. A single port random access memory structure enclosed within the wrapper provides the functional throughput advantage that only a dual port memory device would otherwise make possible.

Abstract: A data processing apparatus including a multiplier unit forming a product from L bits of each two data buses of N bits each N is greater than L. The multiplier forms a N bit output having a first portion which is the L most significant bits of the of product and a second portion which is M other bits not including the L least significant bits of the product, where N is the sum of M and L. In the preferred embodiment the M other bits are derived from other bits of the two input data busses, such as the M other bits of the first input data bus. An arithmetic logic unit performs parallel operations (addition, subtraction, Boolean functions) controlled by the same instructions. This arithmetic logic unit is divisible into a selected number of sections for performing identical operations on independent sections of its inputs. The multiplier unit may form dual products from separate parts of the input data.

Abstract: A palette device controllable by a digital computer with a video memory to produce signals representing color for a video monitor. The palette device includes a multiple-bit input latch for entry of color codes from the video memory, and a look-up table memory for supplying color data words in response to color codes from the input latch. A digital to analog converter responds to color data words to produce an analog color signal. Selection circuitry connected to the input latch and to the look-up table memory supplies the digital to analog converter either with a color data word supplied by the look-up table memory or with a color data word comprised of color codes from the input latch. Improved graphics computer systems, facsimile systems, printer systems and other systems and methods are also disclosed.

Abstract: A method for forming a sum of the absolute value of the difference between each pair of numbers of respective first and second sets of numbers. The method includes forming the difference between a first number of the first set and a second number of the second set. Next this difference is either added to or subtracted from a running sum based upon the sign of this difference. This is repeated until all number pairs are either added to or subtracted from the running sum of absolute values of the differences. The initial subtraction is used to set a status bit in a flag register (211) based upon a less than zero output or the carry-out. The status bit controls whether the difference is added to or subtracted from the running sum. The conditional addition to or subtraction from the running sum may generate a carry-out representing the most significant bit of the running sum. This carry-out is stored and later added to the running sum to recover the most significant overflow bits.

Abstract: An audiovisual communications configuration comprising an interface (28) for receiving from a computer (10) a video signal output by video circuitry (15) of the computer. In this context, the video signal is output by the video circuitry of the computer for displaying an image on a first screen display (18), and the computer includes a microprocessor (15). The audiovisual communications configuration further includes circuitry (64, 66, 68, 70) for coupling a video data signal to a telephone line (40). This circuitry for coupling a video data signal is controllable independently from the microprocessor. The video data signal is representative of the video signal output by the video circuitry. Moreover, the video data signal is configured to be received from the telephone line and decoded to display an image on a second screen display (42) remote from the first screen display. Lastly, the image on the second screen display is representative of the image on the first screen display.

Abstract: A data processing apparatus includes plural data registers, an arithmetic logic unit and a status register. The status register stores a plurality of different types of status bits. These status bits could be a negative status bit, a carry status bit, an overflow status bit and a zero status bit. These status bits are normally set dependent upon the condition of the result generated by the current arithmetic logic unit operation. A status bit protect instruction type permits selection of status bits protected from modification corresponding to the current arithmetic logic unit result. This status bit protect instruction preferably includes individual protect bit corresponding to each status bit. If a protect bit has a first digital state, then the corresponding status bit may be modified corresponding to the current arithmetic logic unit result.

Abstract: A data processing apparatus includes a three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. Data registers (200) store the three data inputs and the arithmetic logic unit output. The second input signal comes from a controllable barrel rotator (235). The rotate amount is a default rotate amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the barrel rotator (235) to supply a multibit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being the rotate amount. The output of the barrel rotator (235) may be stored independently of the arithmetic logic unit (230) result. In the preferred embodiment of this invention, the three input arithmetic logic unit (230) is embodied in a data processor circuits as a part of a multiprocessor integrated circuit (100) used in image processing.

Abstract: A data processing apparatus includes a three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. Data registers (200) store the three data inputs and the arithmetic logic unit output. The second input signal comes from a controllable shifter (235). The shift amount is a default shift amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the shifter (235) to supply a multibit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being the shift amount. The output of the shifter (235) may be stored independently of the arithmetic logic unit (230) result. The third input signal comes from a multiplexer (233) that selects between an instruction specified immediate field, data recalled from a data register or a mask input from a mask generator (239).

Abstract: A synchronous random access memory is arranged to be responsive directly to a system clock signal for operating synchronously with the associated microprocessor. The synchronous random access memory is further arranged to either write-in or read out data in a synchronous burst operation or synchronous wrap operation in addition to synchronous random access operations. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.

Abstract: A memory store operation comes from one of a pair of registers selected by an arithmetic logic unit condition. An instruction logic circuit (250, 660) controls an addressing circuit (120) to store data in a first register into memory if a selected status bit has a first state and to store data in a second register associated with the first register into memory if the selected status bit has a second state in response to a register pair conditional store instruction. The bits may indicate a negative output of the arithmetic logic unit (230), a carry out signal, an overflow, or a zero output. The register pair conditional store instruction designates a particular one of the status bits to control the conditional store. The instruction logic circuit (250, 660) substitutes the selected status bit for a least significant bit of the register number. Thus memory store is from the first register if the status bit is "1" and is from the second register if the status bit is "0".

Abstract: A data processing apparatus including a multiplier unit forming a product from L bits of each two data buses of N bits each N is greater than L. The multiplier forms a N bit output having a first portion which is the L most significant bits of the of product and a second portion which is M other bits not including the L least significant bits of the product, where N is the sum of M and L. In the preferred embodiment the M other bits are derived from other bits of the two input data busses, such as the M other bits of the first input data bus.

Abstract: This invention is a technique for summing plural sections of a single data word. The technique uses a repeated process forming larger and larger partial sums. Initially the single data word is rotated one section. The original single data word and the rotated single data word are masked with a mask having "1's" and "0's" in alternate sections. The mask blocks alternate sections so that adjacent sections of the original data word may be summed on a whole data word basis without any overflow disrupting the partial products. The two masked data words are then summed. This sum results in half as many partial sums as before. Each of these larger partial sums now occupies two original sections of the data word. The process can be repeated for these large partial sums. In the preferred embodiment this technique is used with an arithmetic logic unit (230) capable of forming mixed arithmetic and Boolean combinations of three inputs having a barrel rotator (235) driving one input.

Abstract: A data processing apparatus includes a three input arithmetic logic unit (230) that generates a Boolean combination of the three inputs that is selected by a function signal. The arithmetic logic unit is capable of forming all possible Boolean combinations of the three inputs. Data registers (200) store the three data inputs and the arithmetic logic unit output. The second input signal comes from a controllable shifter (235). The shift amount is a default shift amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the shifter (235) to supply an N bit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being the shift amount. The output of the shifter (235) may be stored independently of the arithmetic logic unit (230) result.

Abstract: A data processing apparatus includes a three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. Data registers (200) store the three data inputs and the arithmetic logic unit output. The second input signal optionally comes from a controllable shifter (235). The shift amount is a default shift amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the shifter (235) to supply an N bit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being the shift amount. The output of the shifter (235) may be stored independently of the arithmetic logic unit (230) result. The third input signal optionally comes from a multiplexer (233) that selects between an instruction specified immediate field, data recalled from a data register or a mask input from a mask generator (239).

Abstract: A synchronous random access memory is arranged to be responsive directly to a system clock signal for operating synchronously with the associated microprocessor. The synchronous random access memory is further arranged to either write-in or read out data in a synchronous burst operation or synchronous wrap operation in addition to synchronous random access operations. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.

Abstract: A three input arithmetic logic unit (230) generates a combination of the three inputs that is selected by a function signal. The second input signal comes from a controllable shifter (235). The shift amount is a default shift amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the shifter (235) to supply a multibit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being the shift amount. The output of the shift (235) may be stored independently of the arithmetic logic unit (230) result. The third input signal comes from a multiplexer (233) that selects between an instruction specified immediate field, data recalled from a data register or a mask input from a mask generator (239). One preferred form of the mask has a number of right justified 1's corresponding to a mask input signal.