Abstract: A tilted nanowire structure is provided which has an increased gate length as compared with a horizontally oriented semiconductor nanowire at the same pitch. Such a structure avoids complexity required for vertical transistors and can be fabricated on a bulk semiconductor substrate without significantly changing/modifying standard transistor fabrication processing.

Abstract: Data associated with a flight, including a flight plan, a vehicle, and/or a pilot is processed via a risk assessment platform to obtain one of more numerical risk values, for example a ground risk value and an air risk value. Based on the processed data, a matrix of risk assessment decisions is generated containing risk related information (such as risk remediation information). Accordingly, based on a consistent set of risk relation information, a predictable and repeatable flight decision (such as a decision whether to fly, or an adjustment to a flight route) can be made. In some instances, the data to be processed is quantitative data collected from one or more third party systems, such as sensor data or geospatial data. The risk assessment platform includes toolkits or services to be used in the processing and transformation of this data to reach a risk assessment decision.

Abstract: A method for manufacturing a semiconductor device includes forming a first vertical transistor on a semiconductor substrate, and forming a second vertical transistor stacked on the first vertical transistor. In the method, a silicide layer is formed on a first drain region of the first vertical transistor and on a second drain region of the second vertical transistor. The silicide layer electrically connects the first and second drain regions to each other.

Abstract: Disclosed herein is a system to detect and characterize individual particles and cells using at least either optic or electric detection as the particle or cell flows through a microfluidic channel. The system also provides for sorting particles and cells or isolating individual particles and cells.

Abstract: Disclosed herein is a system to detect and characterize individual particles and cells using at least either optic or electric detection as the particle or cell flows through a microfluidic channel. The system also provides for sorting particles and cells or isolating individual particles and cells.

Abstract: A platform for unmanned traffic management (UTM) may include a compute system and infrastructure that standardizes and controls aviation data transmitted between service providers, where each service is abstracted from the platform through a service wrapper that enforces the preset data standards. The service wrappers enforce restrictions on the performance and configuration of data from the service provider. The service wrappers are customized to respective services (such as tracking, terrain, or weather), but provide a standard point of interface, security, and trust between the platform and any services directed to provide a similar function. Upon the request of a user or service providers to obtain aviation data, the UTM platform selects a service providing that aviation data, and provides connection data to the user while protecting the security and integrity of the data.

Abstract: Disclosed herein is a system to detect and characterize individual particles and cells using at least either optic or electric detection as the particle or cell flows through a microfluidic channel. The system also provides for sorting particles and cells or isolating individual particles and cells.

Abstract: A first vertical T-FET has a source heavily doped with a source concentration of a source-type dopant, a drain doped with a drain concentration of a drain-type dopant, and a channel between the source and drain. The source, channel, and drain are stacked vertically in a fin or pillar perpendicular to a substrate. A gate stack encompasses the channel sides and has a drain overlap amount overlapping the drain sides and a source overlap amount overlapping the source sides. External contacts electrically connect the gate and source and/or drain. The source-type dopant and the drain-type dopant are opposite dopant types. In some embodiments, a second vertical T-FET is stacked on the first vertical T-FET. Different VT-FET devices are made by changing the materials, doping types and levels, and connections to the sources, channels, and drains. Device characteristics are designed/changed by changing the amount of source and drain overlaps of the gate stack(s).

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with an actively-focused laser beam laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.

Abstract: An electrical device including a vertical transistor device connected to a vertical diode. The vertical diode connected transistor device including a vertically orientated channel. The vertical diode connected transistor device also includes a first diode source/drain region provided by an electrically conductive surface region of a substrate at a first end of the diode vertically orientated channel, and a second diode source/drain region present at a second end of the vertically orientated channel. The vertical diode also includes a diode gate structure in electrical contact with the first diode source/drain region.

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with an actively-focused laser beam laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.

Abstract: A cross-coupled inverter made of nanolayers from a nanosheet stack structure has a left field effect transistor (FET) stack and a right FET stack. The left FET stack has a second left FET stacked on a first left FET. The first and second left FETs have opposite types. The right FET stack has a second right FET stacked on a first right FET. The first and second right FETs have opposite types. The first left and first right FET have a first common source drain (S/D). The left FET stack has a left gate stack surrounding the one or more first left FET channel layers and the one or more second left FET channel layers. The right FET stack has a right gate stack surrounding the one or more first right FET channel layers and the one or more second right FET channel layers. In some embodiments the left/right gate stack has a left/right center gate stack layer and one or more left/right gate stack layers. The center gate stack layers are thicker than the gate stack layers and are between the first and second FETs.

Abstract: A semiconductor device including a first nanosheet stack of two memory cells including a lower nanosheet stack on a substrate including alternating layers of a first work function metal and a semiconductor channel material vertically aligned and stacked one on top of another, and an upper nanosheet stack including alternating layers of a second work function metal and the semiconductor channel material vertically aligned and stacked one on top of another, the upper nanosheet stack vertically aligned and stacked on the lower nanosheet stack, where a first memory cell of the two memory cells including the lower nanosheet stack includes a first threshold voltage and a second memory cell of the two memory cells including the upper nanosheet stack includes a second threshold voltage, where the first threshold voltage is different than the second threshold voltage. Forming a semiconductor device including a first nanosheet stack of two memory cells.

Abstract: Devices, systems, methods, and/or computer-implemented methods that can facilitate a qubit device comprising a vacuum encapsulated Josephson junction are provided. According to an embodiment, a device can comprise a substrate having an encapsulated vacuum cavity provided on the substrate. The device can further comprise one or more superconducting components of a superconducting circuit provided inside the encapsulated vacuum cavity.

Abstract: Devices, systems, methods, and/or computer-implemented methods that can facilitate a qubit device comprising a superconducting circuit provided on an encapsulated vacuum cavity are provided. According to an embodiment, a device can comprise a substrate having an encapsulated vacuum cavity provided on the substrate. The device can further comprise a superconducting circuit provided on the encapsulated vacuum cavity.

Abstract: A Vertical Field Effect Transistor (VFET) and/or a one transistor dynamic random access memory 1T DRAM that has a substrate with a horizontal substrate surface, a source disposed on the horizontal substrate surface, a drain, and a channel. The channel has a channel top, a channel bottom, a first channel side, a second channel side, and two channel ends. The channel top is connected to the drain. The channel bottom is connected to the source. The channel is vertical and perpendicular to the substrate surface. A first gate stack interfaces with the first channel side and a second gate stack interfaces with the second channel side. A single external gate connection electrically connects the first gate stack and the second gate stack A gate bias (voltage) applied on the single external gate connection biases the first channel side in accumulation and biases the second channel side in inversion. The first gate stack is made of a first high-k dielectric layer and a first gate metal layer.

Abstract: A cross-coupled inverter made of nanolayers from a nanosheet stack structure has a left field effect transistor (FET) stack and a right FET stack. The left FET stack has a second left FET stacked on a first left FET. The first and second left FETs have opposite types. The right FET stack has a second right FET stacked on a first right FET. The first and second right FETs have opposite types. The first left and first right FET have a first common source drain (S/D). The left FET stack has a left gate stack surrounding the one or more first left FET channel layers and the one or more second left FET channel layers. The right FET stack has a right gate stack surrounding the one or more first right FET channel layers and the one or more second right FET channel layers. In some embodiments the left/right gate stack has a left/right center gate stack layer and one or more left/right gate stack layers. The center gate stack layers are thicker than the gate stack layers and are between the first and second FETs.

Abstract: A Vertical Function Field Effect Transistor (VIFET) is disclosed with reduced noise and input capacitance and high input impedance. The VIFET has a substrate; a source disposed on the substrate; a drain, and a channel. The vertical channel has one or more channel sidewall surfaces. The channel sidewall surfaces have a total or aggregate channel sidewall surface area. A semiconductor gate grown on one or more of the channel sidewall surfaces has a thickness below 10 nanometers (nm), or between 3 am and 10 om, that reduces transistor noise. The interface surface area between the conductive (e.g. metal) external electrical gate contact and the contacted surface of the semiconductor gate is minimized to further reduce transistor noise.

Abstract: A semiconductor device comprises a substrate, a first source/drain region on the substrate, a first channel region extending vertically with respect to the substrate from the first source/drain region, a second source/drain region on the first channel region, a third source/drain region on the second source/drain region, a second channel region extending vertically with respect to the substrate from the third source/drain region, a fourth source/drain region on the second channel region, a first gate region formed around from the first channel region, and a second gate region formed around the second channel region.

Abstract: In an embodiment, a semiconductor processing tool for implementing hybrid laser and plasma dicing of a substrate is provided. The semiconductor processing tool comprises a transfer module, where the transfer module comprises a track robot for handling the substrate, and a loadlock attached to the transfer module. In an embodiment, the loadlock comprises a linear transfer system for handling the substrate. In an embodiment, the processing tool further comprises a processing chamber attached to the loadlock, wherein the linear transfer system of the loadlock is configured to insert and remove the substrate from the processing chamber.