Patents by Inventor KARTHIK JAMBUNATHAN

KARTHIK JAMBUNATHAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11757037
    Abstract: Epitaxial oxide plugs are described for imposing strain on a channel region of a proximate channel region of a transistor. The oxide plugs form epitaxial and coherent contact with one or more source and drain regions adjacent to the strained channel region. The epitaxial oxide plugs can be used to either impart strain to an otherwise unstrained channel region (e.g., for a semiconductor body that is unstrained relative to an underlying buffer layer), or to restore, maintain, or increase strain within a channel region of a previously strained semiconductor body. The epitaxial crystalline oxide plugs have a perovskite crystal structure in some embodiments.
    Type: Grant
    Filed: January 6, 2022
    Date of Patent: September 12, 2023
    Assignee: Intel Corporation
    Inventors: Karthik Jambunathan, Biswajeet Guha, Anupama Bowonder, Anand S. Murthy, Tahir Ghani
  • Patent number: 11735670
    Abstract: Integrated circuit transistor structures and processes are disclosed that reduce n-type dopant diffusion, such as phosphorous or arsenic, from the source region and the drain region of a germanium n-MOS device into adjacent channel regions during fabrication. The n-MOS transistor device may include at least 70% germanium (Ge) by atomic percentage. In an example embodiment, source and drain regions of the transistor are formed using a low temperature, non-selective deposition process of n-type doped material. In some embodiments, the low temperature deposition process is performed in the range of 450 to 600 degrees C. The resulting structure includes a layer of doped mono-crystyalline silicon (Si), or silicon germanium (SiGe), on the source/drain regions. The structure also includes a layer of doped amorphous Si:P (or SiGe:P) on the surfaces of a shallow trench isolation (STI) region and the surfaces of contact trench sidewalls.
    Type: Grant
    Filed: October 8, 2021
    Date of Patent: August 22, 2023
    Assignee: Intel Corporation
    Inventors: Glenn A. Glass, Anand S. Murthy, Karthik Jambunathan, Cory C. Bomberger, Tahir Ghani, Jack T. Kavalieros, Benjamin Chu-Kung, Seung Hoon Sung, Siddharth Chouksey
  • Patent number: 11699756
    Abstract: Integrated circuit transistor structures are disclosed that reduce n-type dopant diffusion, such as phosphorous or arsenic, from the source region and the drain region of a germanium n-MOS device into adjacent shallow trench isolation (STI) regions during fabrication. The n-MOS transistor device may include at least 75% germanium by atomic percentage. In an example embodiment, the structure includes an intervening diffusion barrier deposited between the n-MOS transistor and the STI region to provide dopant diffusion reduction. In some embodiments, the diffusion barrier may include silicon dioxide with carbon concentrations between 5 and 50% by atomic percentage. In some embodiments, the diffusion barrier may be deposited using chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) techniques to achieve a diffusion barrier thickness in the range of 1 to 5 nanometers.
    Type: Grant
    Filed: December 2, 2021
    Date of Patent: July 11, 2023
    Assignee: Intel Corporation
    Inventors: Glenn A. Glass, Anand S. Murthy, Karthik Jambunathan, Cory C. Bomberger, Tahir Ghani, Jack T. Kavalieros, Benjamin Chu-Kung, Seung Hoon Sung, Siddharth Chouksey
  • Publication number: 20230207317
    Abstract: In one embodiment, an integrated circuit includes a substrate, a buffer layer, a source region, a drain region, a channel region, and a gate structure. The substrate includes silicon. The buffer layer is above the substrate and includes a semiconductor material having defects near an interface with the substrate. The buffer layer also includes ions implanted among the defects. The source region and drain region are above the buffer layer, and the channel region is above the buffer layer and between the source and drain regions. The gate structure above the channel region.
    Type: Application
    Filed: December 23, 2021
    Publication date: June 29, 2023
    Applicant: Intel Corporation
    Inventors: Cory C. Bomberger, Karthik Jambunathan, Anand Murthy, Ju Nam, Tahir Ghani
  • Patent number: 11588017
    Abstract: Particular embodiments described herein provide for an electronic device that can include a nanowire channel. The nanowire channel can include nanowires and the nanowires can be about fifteen (15) or less angstroms apart. The nanowire channel can include more than ten (10) nanowires and can be created from a MXene material.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: February 21, 2023
    Assignee: Intel Corporation
    Inventors: Glenn A. Glass, Chandra S. Mohapatra, Anand S. Murthy, Karthik Jambunathan
  • Patent number: 11538905
    Abstract: Techniques are disclosed for forming nanowire transistors employing carbon-based layers. Carbon is added to the sacrificial layers and/or non-sacrificial layers of a multilayer stack forming one or more nanowires in the transistor channel region. Such carbon-based layers reduce or prevent diffusion and intermixing of the sacrificial and non-sacrificial portions of the multilayer stack. The reduction of diffusion/intermixing can allow for the originally formed layers to effectively maintain their original thicknesses, thereby enabling the formation of relatively more nanowires for a given channel region height because of the more accurate processing scheme. The techniques can be used to benefit group IV semiconductor material nanowire devices (e.g., devices including Si, Ge, and/or SiGe) and can also assist with the selective etch processing used to form the nanowires.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: December 27, 2022
    Assignee: Intel Corporation
    Inventors: Glenn A. Glass, Anand S. Murthy, Nabil G. Mistkawi, Karthik Jambunathan, Tahir Ghani
  • Publication number: 20220384704
    Abstract: Materials with etch selectivity with respect to one another and one or more additional etch-stop layers are used in a Josephson junction structure to allow for integration with a Josephson junction with supporting structures such as resistors. Selective etch processes compatible with high volume manufacturing are used to pattern various layers of the Josephson junction structure to provide a Josephson junction, which is electrically coupled to a support structure.
    Type: Application
    Filed: May 28, 2021
    Publication date: December 1, 2022
    Inventors: Richard P. ROUSE, Karthik JAMBUNATHAN, Susan E. SHORE, Jeremy WARREN, Manan PATEL, Brian BENTON, Kan MI, Kenneth FLUGAUR, Alexander CHOV, Bryan SMITH
  • Patent number: 11482457
    Abstract: Techniques are described for forming strained fins for co-integrated n-MOS and p-MOS devices that include one or more defect trapping layers that prevent defects from migrating into channel regions of the various co-integrated n-MOS and p-MOS devices. A defect trapping layer can include one or more patterned dielectric layers that define aspect ratio trapping trenches. An alternative defect trapping layer can include a superlattice structure of alternating, epitaxially mismatched materials that provides an energetic barrier to the migration of defect. Regardless, the defect trapping layer can prevent dislocations, stacking faults, and other crystallographic defects present in a relaxed silicon germanium layer from migrating into strained n-MOS and p-MOS channel regions grown thereon.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: October 25, 2022
    Assignee: Intel Corporation
    Inventors: Karthik Jambunathan, Cory C. Bomberger, Anand S. Murthy
  • Publication number: 20220336634
    Abstract: Embodiments herein describe techniques, systems, and method for a semiconductor device. A nanowire transistor may include a channel region including a nanowire above a substrate, a source electrode coupled to a first end of the nanowire through a first etch stop layer, and a drain electrode coupled to a second end of the nanowire through a second etch stop layer. A gate electrode may be above the substrate to control conductivity in at least a portion of the channel region. A first spacer may be above the substrate between the gate electrode and the source electrode, and a second spacer may be above the substrate between the gate electrode and the drain electrode. A gate dielectric layer may be between the channel region and the gate electrode. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: June 29, 2022
    Publication date: October 20, 2022
    Inventors: Karthik JAMBUNATHAN, Biswajeet GUHA, Anand S. MURTHY, Tahir GHANI
  • Patent number: 11444166
    Abstract: Techniques are disclosed for backside source/drain (S/D) replacement for semiconductor devices with metallization on both sides (MOBS). The techniques described herein provide methods to recover or otherwise facilitate low contact resistance, thereby reducing or eliminating parasitic external resistance that degrades transistor performance. In some cases, the techniques include forming sacrificial S/D material and a seed layer during frontside processing of a device layer including one or more transistor devices. The device layer can then be inverted and bonded to a host wafer. A backside reveal of the device layer can then be performed via grinding, etching, and/or CMP processes. The sacrificial S/D material can then be removed through backside S/D contact trenches using the seed layer as an etch stop, followed by the formation of relatively highly doped final S/D material grown from the seed layer, to provide enhanced ohmic contact properties. Other embodiments may be described and/or disclosed.
    Type: Grant
    Filed: October 28, 2020
    Date of Patent: September 13, 2022
    Assignee: Intel Corporation
    Inventors: Glenn A. Glass, Karthik Jambunathan, Anand S. Murthy, Chandra S. Mohapatra, Patrick Morrow, Mauro J. Kobrinsky
  • Patent number: 11430787
    Abstract: Techniques for forming contacts comprising at least one crystal on source and drain (S/D) regions of semiconductor devices are described. Crystalline S/D contacts can be formed so as to conform to some or all of the top and side surfaces of the S/D regions. Crystalline S/D contacts of the present disclosure are formed by selectively depositing precursor on an exposed portion of one or more S/D regions. The precursor are then reacted in situ on the exposed portion of the S/D region. This reaction forms the conductive, crystalline S/D contact that conforms to the surface of the S/D regions.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: August 30, 2022
    Assignee: Intel Corporation
    Inventors: Karthik Jambunathan, Scott J. Maddox, Cory C. Bomberger, Anand S. Murthy
  • Patent number: 11411096
    Abstract: Embodiments herein describe techniques, systems, and method for a semiconductor device. A nanowire transistor may include a channel region including a nanowire above a substrate, a source electrode coupled to a first end of the nanowire through a first etch stop layer, and a drain electrode coupled to a second end of the nanowire through a second etch stop layer. A gate electrode may be above the substrate to control conductivity in at least a portion of the channel region. A first spacer may be above the substrate between the gate electrode and the source electrode, and a second spacer may be above the substrate between the gate electrode and the drain electrode. A gate dielectric layer may be between the channel region and the gate electrode. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: August 9, 2022
    Assignee: Intel Corporation
    Inventors: Karthik Jambunathan, Biswajeet Guha, Anand S. Murthy, Tahir Ghani
  • Patent number: 11404575
    Abstract: Techniques are disclosed for forming diverse transistor channel materials enabled by a thin, inverse-graded, germanium (Ge)-based layer. The thin, inverse-graded, Ge-based layer (e.g., having a thickness of at most 500 nm) can then serve as a template for the growth of compressively strained PMOS channel material and tensile strained NMOS channel material to achieve gains in hole and electron mobility, respectively, in the channel regions of the devices. Such a relatively thin Ge-based layer can be formed with suitable surface quality/relaxation levels due to the inverse grading of the Ge concentration in the layer, where the Ge concentration is relatively greatest near the substrate and relatively lowest near the overlying channel material layer. In addition to the inverse-graded Ge concentration, the Ge-based layer may be characterized by the nucleation, and predominant containment, of defects at/near the interface between the substrate and the Ge-based layer.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: August 2, 2022
    Assignee: Intel Corporation
    Inventors: Karthik Jambunathan, Cory C. Bomberger, Glenn A. Glass, Anand S. Murthy, Ju H. Nam, Tahir Ghani
  • Patent number: 11335600
    Abstract: A method including forming a fin of a nonplanar device on a substrate, the fin including a second layer between a first layer and a third layer; replacing the second layer with a dielectric material; and forming a gate stack on a channel region of the fin. An apparatus including a first multigate device on a substrate including a fin including a conducting layer on a dielectric layer, a gate stack disposed on the conducting layer in a channel region of the fin, and a source and a drain formed in the fin, and a second multigate device on the substrate including a fin including a first conducting layer and a second conducting layer separated by a dielectric layer, a gate stack disposed the first conducting layer and the second conducting layer in a channel region of the fin, and a source and a drain formed in the fin.
    Type: Grant
    Filed: June 27, 2015
    Date of Patent: May 17, 2022
    Assignee: Intel Corporation
    Inventors: Seiyon Kim, Jack T. Kavalieros, Anand S. Murthy, Glenn A. Glass, Karthik Jambunathan
  • Publication number: 20220131007
    Abstract: Epitaxial oxide plugs are described for imposing strain on a channel region of a proximate channel region of a transistor. The oxide plugs form epitaxial and coherent contact with one or more source and drain regions adjacent to the strained channel region. The epitaxial oxide plugs can be used to either impart strain to an otherwise unstrained channel region (e.g., for a semiconductor body that is unstrained relative to an underlying buffer layer), or to restore, maintain, or increase strain within a channel region of a previously strained semiconductor body. The epitaxial crystalline oxide plugs have a perovskite crystal structure in some embodiments.
    Type: Application
    Filed: January 6, 2022
    Publication date: April 28, 2022
    Inventors: Karthik JAMBUNATHAN, Biswajeet GUHA, Anupama BOWONDER, Anand S. MURTHY, Tahir GHANI
  • Publication number: 20220093797
    Abstract: Integrated circuit transistor structures are disclosed that reduce n-type dopant diffusion, such as phosphorous or arsenic, from the source region and the drain region of a germanium n-MOS device into adjacent shallow trench isolation (STI) regions during fabrication. The n-MOS transistor device may include at least 75% germanium by atomic percentage. In an example embodiment, the structure includes an intervening diffusion barrier deposited between the n-MOS transistor and the STI region to provide dopant diffusion reduction. In some embodiments, the diffusion barrier may include silicon dioxide with carbon concentrations between 5 and 50% by atomic percentage. In some embodiments, the diffusion barrier may be deposited using chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) techniques to achieve a diffusion barrier thickness in the range of 1 to 5 nanometers.
    Type: Application
    Filed: December 2, 2021
    Publication date: March 24, 2022
    Inventors: Glenn A. GLASS, Anand S. MURTHY, Karthik JAMBUNATHAN, Cory C. BOMBERGER, Tahir GHANI, Jack T. KAVALIEROS, Benjamin CHU-KUNG, Seung Hoon SUNG, Siddharth CHOUKSEY
  • Patent number: 11264501
    Abstract: Techniques and mechanisms for imposing stress on a channel region of an NMOS transistor. In an embodiment, a fin structure on a semiconductor substrate includes two source or drain regions of the transistor, wherein a channel region of the transistor is located between the source or drain regions. At least on such source or drain region includes a doped silicon germanium (SiGe) compound, wherein dislocations in the SiGe compound result in the at least one source or drain region exerting a tensile stress on the channel region. In another embodiment, source or drain regions of a transistor each include a SiGe compound which comprises at least 50 wt % germanium.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: March 1, 2022
    Assignee: Intel Corporation
    Inventors: Rishabh Mehandru, Anand Murthy, Karthik Jambunathan, Cory Bomberger
  • Patent number: 11251302
    Abstract: Epitaxial oxide plugs are described for imposing strain on a channel region of a proximate channel region of a transistor. The oxide plugs form epitaxial and coherent contact with one or more source and drain regions adjacent to the strained channel region. The epitaxial oxide plugs can be used to either impart strain to an otherwise unstrained channel region (e.g., for a semiconductor body that is unstrained relative to an underlying buffer layer), or to restore, maintain, or increase strain within a channel region of a previously strained semiconductor body. The epitaxial crystalline oxide plugs have a perovskite crystal structure in some embodiments.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: February 15, 2022
    Assignee: Intel Corporation
    Inventors: Karthik Jambunathan, Biswajeet Guha, Anupama Bowonder, Anand S. Murthy, Tahir Ghani
  • Publication number: 20220037530
    Abstract: Integrated circuit transistor structures and processes are disclosed that reduce n-type dopant diffusion, such as phosphorous or arsenic, from the source region and the drain region of a germanium n-MOS device into adjacent channel regions during fabrication. The n-MOS transistor device may include at least 70% germanium (Ge) by atomic percentage. In an example embodiment, source and drain regions of the transistor are formed using a low temperature, non-selective deposition process of n-type doped material. In some embodiments, the low temperature deposition process is performed in the range of 450 to 600 degrees C. The resulting structure includes a layer of doped mono-crystyalline silicon (Si), or silicon germanium (SiGe), on the source/drain regions. The structure also includes a layer of doped amorphous Si:P (or SiGe:P) on the surfaces of a shallow trench isolation (STI) region and the surfaces of contact trench sidewalls.
    Type: Application
    Filed: October 8, 2021
    Publication date: February 3, 2022
    Inventors: Glenn A. GLASS, Anand S. MURTHY, Karthik JAMBUNATHAN, Cory C. BOMBERGER, Tahir GHANI, Jack T. KAVALIEROS, Benjamin CHU-KUNG, Seung Hoon SUNG, Siddharth CHOUKSEY
  • Patent number: 11222977
    Abstract: Integrated circuit transistor structures are disclosed that reduce n-type dopant diffusion, such as phosphorous or arsenic, from the source region and the drain region of a germanium n-MOS device into adjacent shallow trench isolation (STI) regions during fabrication. The n-MOS transistor device may include at least 75% germanium by atomic percentage. In an example embodiment, the structure includes an intervening diffusion barrier deposited between the n-MOS transistor and the STI region to provide dopant diffusion reduction. In some embodiments, the diffusion barrier may include silicon dioxide with carbon concentrations between 5 and 50% by atomic percentage. In some embodiments, the diffusion barrier may be deposited using chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) techniques to achieve a diffusion barrier thickness in the range of 1 to 5 nanometers.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: January 11, 2022
    Assignee: Intel Corporation
    Inventors: Glenn A. Glass, Anand S. Murthy, Karthik Jambunathan, Cory C. Bomberger, Tahir Ghani, Jack T. Kavalieros, Benjamin Chu-Kung, Seung Hoon Sung, Siddharth Chouksey