Patents by Inventor Karuna NIDHI
Karuna NIDHI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11810872Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a gate disposed on the semiconductor substrate. The semiconductor device structure also includes a source doped region and a drain doped region on two opposite sides of the gate. The semiconductor device structure further includes a source protective circuit and a drain protective circuit. From a side perspective view, a first drain conductive element of the source protective circuit partially overlaps a first source conductive element of the drain protective circuit.Type: GrantFiled: August 29, 2022Date of Patent: November 7, 2023Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Jian-Hsing Lee, Shao-Chang Huang, Chih-Hsuan Lin, Yu-Kai Wang, Karuna Nidhi, Hwa-Chyi Chiou
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Publication number: 20220415828Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a gate disposed on the semiconductor substrate. The semiconductor device structure also includes a source doped region and a drain doped region on two opposite sides of the gate. The semiconductor device structure further includes a source protective circuit and a drain protective circuit. From a side perspective view, a first drain conductive element of the source protective circuit partially overlaps a first source conductive element of the drain protective circuit.Type: ApplicationFiled: August 29, 2022Publication date: December 29, 2022Applicant: Vanguard International Semiconductor CorporationInventors: Jian-Hsing LEE, Shao-Chang HUANG, Chih-Hsuan LIN, Yu-Kai WANG, Karuna NIDHI, Hwa-Chyi CHIOU
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Patent number: 11527607Abstract: A semiconductor device includes at least one transistor, a shallow well region, a guard ring, and a plurality of first and second doped regions. The transistor is on a substrate and includes a source structure, a gate structure, and a drain structure. The shallow well region surrounds the transistor. The shallow well region has a first conductivity type. The guard ring surrounds the shallow well region. The guard ring has the first conductivity type. The first and second doped regions are disposed on the guard ring and surround the well region. The first doped regions and the second doped regions are alternately arranged in a shape of a loop. Each of the first doped regions and each of the second doped regions have opposite conductivity types.Type: GrantFiled: December 14, 2020Date of Patent: December 13, 2022Assignee: Vanguard International Semiconductor CorporationInventors: Karuna Nidhi, Chih-Hsuan Lin, Jian-Hsing Lee, Hwa-Chyi Chiou
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Patent number: 11476207Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a gate disposed on the semiconductor substrate. The semiconductor device structure also includes a source doped region and a drain doped region on two opposite sides of the gate. The semiconductor device structure further includes a source protective circuit and a drain protective circuit. From a side perspective view, a first drain conductive element of the source protective circuit partially overlaps a first source conductive element of the drain protective circuit.Type: GrantFiled: October 23, 2019Date of Patent: October 18, 2022Assignee: Vanguard International Semiconductor CorporationInventors: Jian-Hsing Lee, Shao-Chang Huang, Chih-Hsuan Lin, Yu-Kai Wang, Karuna Nidhi, Hwa-Chyi Chiou
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Publication number: 20220190106Abstract: A semiconductor device includes at least one transistor, a shallow well region, a guard ring, and a plurality of first and second doped regions. The transistor is on a substrate and includes a source structure, a gate structure, and a drain structure. The shallow well region surrounds the transistor. The shallow well region has a first conductivity type. The guard ring surrounds the shallow well region. The guard ring has the first conductivity type. The first and second doped regions are disposed on the guard ring and surround the well region. The first doped regions and the second doped regions are alternately arranged in a shape of a loop. Each of the first doped regions and each of the second doped regions have opposite conductivity types.Type: ApplicationFiled: December 14, 2020Publication date: June 16, 2022Applicant: Vanguard International Semiconductor CorporationInventors: Karuna NIDHI, Chih-Hsuan LIN, Jian-Hsing LEE, Hwa-Chyi CHIOU
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Publication number: 20210125943Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a gate disposed on the semiconductor substrate. The semiconductor device structure also includes a source doped region and a drain doped region on two opposite sides of the gate. The semiconductor device structure further includes a source protective circuit and a drain protective circuit. From a side perspective view, a first drain conductive element of the source protective circuit partially overlaps a first source conductive element of the drain protective circuit.Type: ApplicationFiled: October 23, 2019Publication date: April 29, 2021Applicant: Vanguard International Semiconductor CorporationInventors: Jian-Hsing LEE, Shao-Chang HUANG, Chih-Hsuan LIN, Yu-Kai WANG, Karuna NIDHI, Hwa-Chyi CHIOU
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Patent number: 9997510Abstract: The invention provides a semiconductor device layout structure disposed in an active region. The semiconductor device layout structure includes a first well region having a first conduction type. A second well region having a second conduction type opposite the first conduction type is disposed adjacent to and enclosing the first well region. A first doped region having the second conduction type is disposed within the first well region. A second doped region having the second conduction type is disposed within the first well region. The second doped region is separated from and surrounds the first doped region. A third doped region having the second conduction type is disposed within the second well region.Type: GrantFiled: September 9, 2015Date of Patent: June 12, 2018Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Chi-Li Tu, Ching-Wen Wang, Karuna Nidhi
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Patent number: 9722097Abstract: A semiconductor device is provided. The semiconductor device includes a substrate; a well region disposed in the substrate; an isolation structure surrounding an active region in the well region; a source region disposed in the well region; a drain region disposed in the well region; a second conductive type first doped region disposed in the well region and disposed along a periphery of the active region; a second conductive type second doped region disposed in the well region and under the source region, the drain region and the second conductive type first doped region, wherein the second conductive type second doped region is in direct contact with the second conductive type first doped region; a source electrode; a drain electrode and a gate electrode. The present disclosure also provides a method for manufacturing the semiconductor device.Type: GrantFiled: September 16, 2015Date of Patent: August 1, 2017Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Karuna Nidhi, Federico Agustin Altolaguirre, Ming-Dou Ker, Geeng-Lih Lin
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Publication number: 20170077316Abstract: A semiconductor device is provided. The semiconductor device includes a substrate; a well region disposed in the substrate; an isolation structure surrounding an active region in the well region; a source region disposed in the well region; a drain region disposed in the well region; a second conductive type first doped region disposed in the well region and disposed along a periphery of the active region; a second conductive type second doped region disposed in the well region and under the source region, the drain region and the second conductive type first doped region, wherein the second conductive type second doped region is in direct contact with the second conductive type first doped region; a source electrode; a drain electrode and a gate electrode. The present disclosure also provides a method for manufacturing the semiconductor device.Type: ApplicationFiled: September 16, 2015Publication date: March 16, 2017Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Karuna NIDHI, Federico Agustin ALTOLAGUIRRE, Ming-Dou KER, Geeng-Lih LIN
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Publication number: 20170069620Abstract: The invention provides a semiconductor device layout structure disposed in an active region. The semiconductor device layout structure includes a first well region having a first conduction type. A second well region having a second conduction type opposite the first conduction type is disposed adjacent to and enclosing the first well region. A first doped region having the second conduction type is disposed within the first well region. A second doped region having the second conduction type is disposed within the first well region. The second doped region is separated from and surrounds the first doped region. A third doped region having the second conduction type is disposed within the second well region.Type: ApplicationFiled: September 9, 2015Publication date: March 9, 2017Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Chi-Li TU, Ching-Wen WANG, Karuna NIDHI
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Patent number: 9437591Abstract: A cross-domain electrostatic protection device having four embedded silicon controlled rectifiers (a QSCR structure) embedded in a single cell. Two grounded-gate NMOS transistors are embedded into the cross-domain electrostatic protection device for reducing trigger voltage of the QSCR structure. Furthermore, an external trigger circuit and a bias circuit are applied to the cross-domain electrostatic protection device to reduce trigger voltage of the QSCR structure and leakage current.Type: GrantFiled: September 9, 2015Date of Patent: September 6, 2016Assignee: Vanguard International Semiconductor CorporationInventors: Karuna Nidhi, Federico Agustin Altolaguirre, Ming-Dou Ker, Geeng-Lih Lin
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Patent number: 9048115Abstract: A method for fabricating a semiconductor device is provided. An epitaxial layer is grown on a substrate, wherein the epitaxial layer and the substrate have a first conductivity type. A trench is formed in the epitaxial layer. A barrier region is formed at a bottom of the trench. A doped region of a second conductivity type is formed in the epitaxial layer and surrounds sidewalls of the trench, wherein the barrier region prevents a dopant used for forming the doped region from reaching the epitaxial layer under the barrier region. The trench is filled with a dielectric material. A pair of polysilicon gates is formed on the epitaxial layer and on both sides of the trench.Type: GrantFiled: October 26, 2012Date of Patent: June 2, 2015Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Tsung-Hsiung Lee, Shang-Hui Tu, Gene Sheu, Neelam Agarwal, Karuna Nidhi, Chia-Hao Lee, Rudy Octavius Sihombing
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Publication number: 20140117436Abstract: A method for fabricating a semiconductor device is provided. An epitaxial layer is grown on a substrate, wherein the epitaxial layer and the substrate have a first conductivity type. A trench is formed in the epitaxial layer. A barrier region is formed at a bottom of the trench. A doped region of a second conductivity type is formed in the epitaxial layer and surrounds sidewalls of the trench, wherein the barrier region prevents a dopant used for forming the doped region from reaching the epitaxial layer under the barrier region. The trench is filled with a dielectric material. A pair of polysilicon gates is formed on the epitaxial layer and on both sides of the trench.Type: ApplicationFiled: October 26, 2012Publication date: May 1, 2014Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Tsung-Hsiung LEE, Shang-Hui TU, Gene SHEU, Neelam AGARWAL, Karuna NIDHI, Chia-Hao LEE, Rudy Octavius SIHOMBING