Patents by Inventor Kathryn W. Guarini
Kathryn W. Guarini has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7960790Abstract: A double-gate transistor having front (upper) and back gates that are aligned laterally is provided. The double-gate transistor includes a back gate thermal oxide layer below a device layer; a back gate electrode below a back gate thermal oxide layer; a front gate thermal oxide above the device layer; a front gate electrode layer above the front gate thermal oxide and vertically aligned with the back gate electrode; and a transistor body disposed above the back gate thermal oxide layer, symmetric with the first gate. The back gate electrode has a layer of oxide formed below the transistor body and on either side of a central portion of the back gate electrode, thereby positioning the back gate self-aligned with the front gate. The transistor also includes source and drain electrodes on opposite sides of said transistor body.Type: GrantFiled: May 13, 2008Date of Patent: June 14, 2011Assignee: International Business Machines CorporationInventors: Omer H. Dokumaci, Bruce B. Doris, Kathryn W. Guarini, Suryanararyan G. Hegde, Meikei Ieong, Erin Catherine Jones
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Patent number: 7790538Abstract: A structure and method of fabrication for PFET devices in a compressively strained Ge layer is disclosed. The fabrication method of such devices is compatible with standard CMOS technology and it is fully scalable. The processing includes selective epitaxial depositions of an over 50% Ge content buffer layer, a pure Ge layer, and a SiGe top layer. Fabricated buried channel PMOS devices hosted in the compressively strained Ge layer show superior device characteristics relative to similar Si devices.Type: GrantFiled: May 10, 2008Date of Patent: September 7, 2010Assignee: International Business Machines CorporationInventors: Huiling Shang, Meikei Ieong, Jack Oon Chu, Kathryn W. Guarini
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Patent number: 7723207Abstract: A three dimensional (3D) integrated circuit (IC), 3D IC chip and method of fabricating a 3D IC chip. The chip includes multiple layers of circuits, e.g., silicon insulator (SOI) CMOS IC layers, each including circuit elements. The layers may be formed in parallel and one layer attached to another to form a laminated 3D chip.Type: GrantFiled: April 19, 2007Date of Patent: May 25, 2010Assignee: International Business Machines CorporationInventors: Syed M. Alam, Ibrahim M. Elfadel, Kathryn W Guarini, Meikei Ieong, Prabhakar N. Kudva, David S. Kung, Mark A. Lavin, Arifur Rahman
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Patent number: 7713807Abstract: An integrated semiconductor structure containing at least one device formed upon a first crystallographic surface that is optimal for that device, while another device is formed upon a second different crystallographic surface that is optimal for the other device is provided. The method of forming the integrated structure includes providing a bonded substrate including at least a first semiconductor layer of a first crystallographic orientation and a second semiconductor layer of a second different crystallographic orientation. A portion of the bonded substrate is protected to define a first device area, while another portion of the bonded substrate is unprotected. The unprotected portion of the bonded substrate is then etched to expose a surface of the second semiconductor layer and a semiconductor material is regrown on the exposed surface. Following planarization, a first semiconductor device is formed in the first device region and a second semiconductor device is formed on the regrown material.Type: GrantFiled: December 18, 2007Date of Patent: May 11, 2010Assignee: International Business Machines CorporationInventors: Bruce B. Doris, Kathryn W. Guarini, Meikei Ieong, Shreesh Narasimha, Kern Rim, Jeffrey W. Sleight, Min Yang
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Patent number: 7453123Abstract: A double-gate transistor having front (upper) and back gates that are aligned laterally is provided. The double-gate transistor includes a back gate thermal oxide layer below a device layer; a back gate electrode below a back gate thermal oxide layer; a front gate thermal oxide above the device layer: a front gate electrode layer above the front gate thermal oxide and vertically aligned with the back gate electrode; and a transistor body disposed above the back gate thermal oxide layer, symmetric with the first gate. The back gate electrode has a layer of oxide formed below the transistor body and on either side of a central portion of the back gate electrode, thereby positioning the back gate self-aligned with the front gate. The transistor also includes source and drain electrodes on opposite sides of said transistor body.Type: GrantFiled: February 16, 2007Date of Patent: November 18, 2008Assignee: International Business Machines CorporationInventors: Omer H. Dokumaci, Bruce B. Doris, Kathryn W. Guarini, Suryanarayan G. Hegde, Meikei Ieong, Erin Catherine Jones
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Publication number: 20080248616Abstract: A structure and method of fabrication for PFET devices in a compressively strained Ge layer is disclosed. The fabrication method of such devices is compatible with standard CMOS technology and it is fully scalable. The processing includes selective epitaxial depositions of an over 50% Ge content buffer layer, a pure Ge layer, and a SiGe top layer. Fabricated buried channel PMOS devices hosted in the compressively strained Ge layer show superior device characteristics relative to similar Si devices.Type: ApplicationFiled: May 10, 2008Publication date: October 9, 2008Applicant: International Business Machines CorporationInventors: Huiling Shang, Meikei Ieong, Jack Oon Chu, Kathryn W. Guarini
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Publication number: 20080246090Abstract: A double-gate transistor having front (upper) and back gates that are aligned laterally is provided. The double-gate transistor includes a back gate thermal oxide layer below a device layer; a back gate electrode below a back gate thermal oxide layer; a front gate thermal oxide above the device layer; a front gate electrode layer above the front gate thermal oxide and vertically aligned with the back gate electrode; and a transistor body disposed above the back gate thermal oxide layer, symmetric with the first gate. The back gate electrode has a layer of oxide formed below the transistor body and on either side of a central portion of the back gate electrode, thereby positioning the back gate self-aligned with the front gate. The transistor also includes source and drain electrodes on opposite sides of said transistor body.Type: ApplicationFiled: May 13, 2008Publication date: October 9, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Omer H. Dokumaci, Bruce B. Doris, Kathryn W. Guarini, Suryanarayan G. Hegde, MeiKei Ieong, Erin Catherine Jones
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Publication number: 20080165521Abstract: A three-dimensional architecture chip includes a base chip including a unit integrated thereon and configured to perform electrical signal operations. An active layer is separately fabricated from the base layer. The active layer includes a component to service the unit of the base chip. The active layer is bonded to the base chip such that the component is aligned in vertical proximity of the unit. An electrical connection connects the unit to the component through vertical layers of at least one of the base chip and the active layer.Type: ApplicationFiled: January 9, 2007Publication date: July 10, 2008Inventors: KERRY BERNSTEIN, Paul William Coteus, Ibrahim (Abe) M. Elfadel, Philip George Emma, Kathryn W. Guarini, Thomas Fleischman, Allan Mark Hartstein, Ruchir Puri, Mark B. Ritter, Jeannine Madelyn Trewhella, Albert M. Young
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Patent number: 7387925Abstract: A structure and method of fabrication for PFET devices in a compressively strained Ge layer is disclosed. The fabrication method of such devices is compatible with standard CMOS technology and it is fully scalable. The processing includes selective epitaxial depositions of an over 50% Ge content buffer layer, a pure Ge layer, and a SiGe top layer. Fabricated buried channel PMOS devices hosted in the compressively strained Ge layer show superior device characteristics relative to similar Si devices.Type: GrantFiled: April 10, 2007Date of Patent: June 17, 2008Assignee: International Business Machines CorporationInventors: Huiling Shang, Meikei Ieong, Jack Oon Chu, Kathryn W. Guarini
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Patent number: 7342301Abstract: A connection device includes a plurality of re-configurable vias that connect a first metal layer to a second metal layer. An actuating element is disposed between the first metal layer and the second metal layer. The actuating element changes the configuration of the plurality of re-configurable vias to change the plurality of re-configurable vias between a conductive state and a non-conductive state.Type: GrantFiled: May 9, 2006Date of Patent: March 11, 2008Assignee: International Business Machines CorporationInventors: David J. Frank, Kathryn W. Guarini, Christopher B. Murray, Xinlin Wang, Hon-Sum Philip Wong
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Patent number: 7329923Abstract: An integrated semiconductor structure containing at least one device formed upon a first crystallographic surface that is optimal for that device, while another device is formed upon a second different crystallographic surface that is optimal for the other device is provided. The method of forming the integrated structure includes providing a bonded substrate including at least a first semiconductor layer of a first crystallographic orientation and a second semiconductor layer of a second different crystallographic orientation. A portion of the bonded substrate is protected to define a first device area, while another portion of the bonded substrate is unprotected. The unprotected portion of the bonded substrate is then etched to expose a surface of the second semiconductor layer and a semiconductor material is regrown on the exposed surface. Following planarization, a first semiconductor device is formed in the first device region and a second semiconductor device is formed on the regrown material.Type: GrantFiled: June 17, 2003Date of Patent: February 12, 2008Assignee: International Business Machines CorporationInventors: Bruce B. Doris, Kathryn W. Guarini, Meikei Ieong, Shreesh Narasimha, Kern Rim, Jeffrey W. Sleight, Min Yang
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Patent number: 7312487Abstract: A three dimensional (3D) integrated circuit (IC), 3D IC chip and method of fabricating a 3D IC chip. The chip includes multiple layers of circuits, e.g., silicon insulator (SOI) CMOS IC layers, each including circuit elements. The layers may be formed in parallel and one layer attached to another to form a laminated 3D chip.Type: GrantFiled: August 16, 2004Date of Patent: December 25, 2007Assignee: International Business Machines CorporationInventors: Syed M. Alam, Ibrahim M. Elfadel, Kathryn W. Guarini, Meikei Ieong, Prabhakar N. Kudva, David S. Kung, Mark A. Lavin, Arifur Rahman
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Patent number: 7244958Abstract: A structure and method of fabrication for PFET devices in a compressively strained Ge layer is disclosed. The fabrication method of such devices is compatible with standard CMOS technology and it is fully scalable. The processing includes selective epitaxial depositions of an over 50% Ge content buffer layer, a pure Ge layer, and a SiGe top layer. Fabricated buried channel PMOS devices hosted in the compressively strained Ge layer show superior device characteristics relative to similar Si devices.Type: GrantFiled: June 24, 2004Date of Patent: July 17, 2007Assignee: International Business Machines CorporationInventors: Huiling Shang, Meikei Ieong, Jack Oon Chu, Kathryn W. Guarini
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Patent number: 7205185Abstract: A double-gate transistor has front (upper) and back gates aligned laterally by a process of forming symmetric sidewalls in proximity to the front gate and then oxidizing the back gate electrode at a temperature of at least 1000 degrees for a time sufficient to relieve stress in the structure, the oxide penetrating from the side of the transistor body to thicken the back gate oxide on the outer edges, leaving an effective thickness of gate oxide at the center, aligned with the front gate electrode. Optionally, an angled implant from the sides of an oxide enhancing species encourages relatively thicker oxide in the outer implanted areas and an oxide-retarding implant across the transistor body retards oxidation in the vertical direction, thereby permitting increase of the lateral extent of the oxidation.Type: GrantFiled: September 15, 2003Date of Patent: April 17, 2007Assignee: International Busniess Machines CorporationInventors: Omer H. Dokumaci, Bruce B. Doris, Kathryn W. Guarini, Suryanarayan G. Hegde, MeiKei Ieong, Erin Catherine Jones
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Patent number: 7187059Abstract: A structure for conducting carriers and method for forming is described incorporating a single crystal substrate of Si or SiGe having an upper surface in the <110> and a psuedomorphic or epitaxial layer of SiGe having a concentration of Ge different than the substrate whereby the psedomorphic layer is under strain. A method for forming semiconductor epitaxial layers is described incorporating the step of forming a psuedomorphic or epitaxial layer in a rapid thermal chemical vapor deposition (RTCVD) tool by increasing the temperature in the tool to about 600° C. and introducing both a Si containing gas and a Ge containing gas.Type: GrantFiled: June 24, 2004Date of Patent: March 6, 2007Assignee: International Business Machines CorporationInventors: Kevin K. Chan, Kathryn W. Guarini, Meikel Ieong, Kern Rim, Min Yang
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Patent number: 7138683Abstract: The present invention provides integrated semiconductor devices that are formed upon an SOI substrate having different crystal orientations that provide optimal performance for a specific device. Specifically, an integrated semiconductor structure including at least an SOI substrate having a top semiconductor layer of a first crystallographic orientation and a semiconductor material of a second crystallographic orientation, wherein the semiconductor material is substantially coplanar and of substantially the same thickness as that of the top semiconductor layer and the first crystallographic orientation is different from the second crystallographic orientation is provided. The SOI substrate is formed by wafer bonding, ion implantation and annealing.Type: GrantFiled: October 18, 2004Date of Patent: November 21, 2006Assignee: International Business Machines CorporationInventors: Kathryn W. Guarini, Meikei Ieong, Leathen Shi, Min Yang
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Patent number: 7074707Abstract: A connection device includes a plurality of re-configurable vias that connect a first metal layer to a second metal layer. An actuating element is disposed between the first metal layer and the second metal layer. The actuating element changes the configuration of the plurality of re-configurable vias to change the plurality of re-configurable vias between a conductive state and a non-conductive state.Type: GrantFiled: September 15, 2003Date of Patent: July 11, 2006Assignee: International Business Machines CorporationInventors: David J. Frank, Kathryn W. Guarini, Christopher B. Murray, Xinlin Wang, Hon-Sum Philip Wong
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Patent number: 6911375Abstract: Described is a method for making silicon on sapphire structures, and devices therefrom. The inventive method of forming integrated circuits on a sapphire substrate comprises the steps of providing a device layer on an oxide layer of a temporary substrate; bonding the device layer to a handling substrate; removing the temporary substrate to provide a structure containing the device layer between the oxide layer and the handling substrate; bonding a sapphire substrate to the oxide layer; removing the handling substrate from the structure; and annealing the final structure to provide a substrate comprising the oxide layer between the device layer and the sapphire substrate. The sapphire substrate may comprise bulk sapphire or may be a conventional substrate material with an uppermost sapphire layer.Type: GrantFiled: June 2, 2003Date of Patent: June 28, 2005Assignee: International Business Machines CorporationInventors: Kathryn W. Guarini, Louis L. Hsu, Leathen Shi, Dinkar V. Singh, Li-Kong Wang
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Publication number: 20040256700Abstract: An integrated semiconductor structure containing at least one device formed upon a first crystallographic surface that is optimal for that device, while another device is formed upon a second different crystallographic surface that is optimal for the other device is provided. The method of forming the integrated structure includes providing a bonded substrate including at least a first semiconductor layer of a first crystallographic orientation and a second semiconductor layer of a second different crystallographic orientation. A portion of the bonded substrate is protected to define a first device area, while another portion of the bonded substrate is unprotected. The unprotected portion of the bonded substrate is then etched to expose a surface of the second semiconductor layer and a semiconductor material is regrown on the exposed surface. Following planarization, a first semiconductor device is formed in the first device region and a second semiconductor device is formed on the regrown material.Type: ApplicationFiled: June 17, 2003Publication date: December 23, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bruce B. Doris, Kathryn W. Guarini, Meikei Ieong, Shreesh Narasimha, Kern Rim, Jeffrey W. Sleight, Min Yang
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Patent number: 6830962Abstract: The present invention provides integrated semiconductor devices that are formed upon an SOI substrate having different crystal orientations that provide optimal performance for a specific device. Specifically, an integrated semiconductor structure including at least an SOI substrate having a top semiconductor layer of a first crystallographic orientation and a semiconductor material of a second crystallographic orientation, wherein the semiconductor material is substantially coplanar and of substantially the same thickness as that of the top semiconductor layer and the first crystallographic orientation is different from the second crystallographic orientation is provided. The SOI substrate is formed by wafer bonding, ion implantation and annealing.Type: GrantFiled: August 5, 2003Date of Patent: December 14, 2004Assignee: International Business Machines CorporationInventors: Kathryn W. Guarini, Meikei Ieong, Leathen Shi, Min Yang