Patents by Inventor Katsuaki Nagata

Katsuaki Nagata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180024785
    Abstract: In accordance with one embodiment, a printing system comprises a memory, a processor and an interface. The processor rewrites the first information contained in the print data stored in the memory and designating a sheet stacking section at an end of a conveyance path of an image forming apparatus. The interface sends the rewritten print data to the image forming apparatus.
    Type: Application
    Filed: October 2, 2017
    Publication date: January 25, 2018
    Inventors: Katsuaki Nagata, Hideyuki Kato, Satoshi Oyama
  • Patent number: 9811291
    Abstract: In accordance with one embodiment, a printing system comprises a memory, a processor and an interface. The processor rewrites the first information contained in the print data stored in the memory and designating a sheet stacking section at an end of a conveyance path of an image forming apparatus. The interface sends the rewritten print data to the image forming apparatus.
    Type: Grant
    Filed: July 10, 2014
    Date of Patent: November 7, 2017
    Assignees: KABUSHIKIK KAISHA TOSHIBA, TOSHIBA TEC KABUSHIKI KAISHA
    Inventors: Katsuaki Nagata, Hideyuki Kato, Satoshi Oyama
  • Publication number: 20160011826
    Abstract: In accordance with one embodiment, a printing system comprises a memory, a processor and an interface. The processor rewrites the first information contained in the print data stored in the memory and designating a sheet stacking section at an end of a conveyance path of an image forming apparatus. The interface sends the rewritten print data to the image forming apparatus.
    Type: Application
    Filed: July 10, 2014
    Publication date: January 14, 2016
    Inventors: Katsuaki Nagata, Hideyuki Kato, Satoshi Oyama
  • Publication number: 20100257411
    Abstract: According to one embodiment, an emulation device includes a storing section that stores model information of an apparatus that can be emulated and an emulator corresponding to the model information, an obtaining section that obtains the model information of the apparatus, a detection section that detects, from the model information in the storing section, model information corresponding to the model information of the apparatus obtained by the obtaining section, and an executing section that activates an emulator of the apparatus corresponding to the detected model information.
    Type: Application
    Filed: April 6, 2010
    Publication date: October 7, 2010
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA TEC KABUSHIKI KAISHA
    Inventors: Kouichi Mase, Yoshiko Suenaga, Kazuto Oonuma, Katsuaki Nagata, Hironori Tanaka, Masamitsu Tsuchiya
  • Patent number: 7502144
    Abstract: A method of generating a second bit map, improved in first-direction resolution, from a first bit map having a plurality of image-forming pixels arranged two-dimensionally, the method comprising a first detection step of detecting first and second edges appearing in a second direction orthogonal to a first direction in a first bit map, and the first addition step of adding at least an edge extending in the first direction, when a portion between the first and second edges permits interpolation, to between third and fourth edges on the second bit map respectively corresponding to the first and second edges so as to effect interpolation between the third and fourth edges. Since the first and second edges, if detected, permit smoothing, a look-up table is not needed, and even a long-range unevenness can be smoothed without a smoothing range being limited to a predetermined region.
    Type: Grant
    Filed: September 20, 2002
    Date of Patent: March 10, 2009
    Assignee: Naltec, Inc.
    Inventors: Yoshiko Nagata, legal representative, Katsuaki Nagata
  • Publication number: 20040239958
    Abstract: A method of generating a second bit map, improved in first-direction resolution, from a first bit map having a plurality of image-forming pixels arranged two-dimensionally, the method comprising a first detection step of detecting first and second edges appearing in a second direction orthogonal to a first direction in a first bit map, and the first addition step of adding at least an edge extending in the first direction, when a portion between the first and second edges permits interpolation, to between third and fourth edges on the second bit map respectively corresponding to the first and second edges so as to effect interpolation between the third and fourth edges. Since the first and second edges, if detected, permit smoothing, a look-up table is not needed, and even a long-range unevenness can be smoothed without a smoothing range being limited to a predetermined region.
    Type: Application
    Filed: March 19, 2004
    Publication date: December 2, 2004
    Inventors: Katsuaki Nagata, Yoshiko Nagata