Patents by Inventor Katsuaki Natori

Katsuaki Natori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210066468
    Abstract: According to at least one embodiment, a semiconductor device includes a plurality of insulating films adjacent to each other. A conductive film is provided between the plurality of insulating films. The conductive film includes molybdenum having a grain diameter substantially the same as a distance from an upper surface to a lower surface of the conductive film.
    Type: Application
    Filed: August 26, 2020
    Publication date: March 4, 2021
    Applicant: KIOXIA CORPORATION
    Inventors: Takayuki BEPPU, Masayuki KITAMURA, Hiroshi TOYODA, Katsuaki NATORI
  • Publication number: 20200258722
    Abstract: A method of manufacturing a semiconductor device includes placing a substrate in a housing, supplying first gas containing molybdenum to the housing to form a film that contains molybdenum, on the substrate, removing the substrate with the formed film from the hosing, and then supplying second gas containing chlorine to the housing to remove molybdenum deposited on a surface of the housing.
    Type: Application
    Filed: August 28, 2019
    Publication date: August 13, 2020
    Inventors: Katsuaki NATORI, Hiroshi TOYODA, Masayuki KITAMURA, Takayuki BEPPU
  • Publication number: 20200091080
    Abstract: A semiconductor device includes a substrate. The semiconductor device further includes a wiring layer provided on the substrate, the wiring layer including a molybdenum layer including oxygen atoms as an impurity.
    Type: Application
    Filed: February 19, 2019
    Publication date: March 19, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Satoshi WAKATSUKI, Katsuaki NATORI
  • Publication number: 20190259621
    Abstract: A production method of a semiconductor device includes introducing a reduction gas for reducing metal to a space containing a target to be used as the semiconductor device. The method also includes introducing a material gas and a first gas simultaneously to the space on a basis of a predetermined partial pressure ratio after introducing the reduction gas, to form a film that contains the metal, on the target. The material gas etches the metal when only the material gas is flowed. The first gas is different from the material gas. The predetermined partial pressure ratio is a ratio of the material gas and the first gas.
    Type: Application
    Filed: July 10, 2018
    Publication date: August 22, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Katsuaki NATORI, Satoshi WAKATSUKI, Masayuki KITAMURA
  • Patent number: 9735347
    Abstract: According to one embodiment, a magnetic memory device includes: a first magnetic layer; a nonmagnetic layer on the first magnetic layer; a second magnetic layer on the nonmagnetic layer; and an insulator film on the nonmagnetic layer surrounding a side surface of the second magnetic layer. The second magnetic layer has an area of a surface facing the nonmagnetic layer smaller than that of the nonmagnetic layer. The nonmagnetic layer includes a first region that is provided between the first magnetic layer and the insulator film. The first region includes an amorphous state.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: August 15, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Koji Yamakawa, Katsuaki Natori, Shinichi Kanoo, Kenji Noma
  • Publication number: 20170062705
    Abstract: According to one embodiment, a magnetic memory device includes: a first magnetic layer; a nonmagnetic layer on the first magnetic layer; a second magnetic layer on the nonmagnetic layer; and an insulator film on the nonmagnetic layer surrounding a side surface of the second magnetic layer. The second magnetic layer has an area of a surface facing the nonmagnetic layer smaller than that of the nonmagnetic layer. The nonmagnetic layer includes a first region that is provided between the first magnetic layer and the insulator film. The first region includes an amorphous state.
    Type: Application
    Filed: March 9, 2016
    Publication date: March 2, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Koji YAMAKAWA, Katsuaki NATORI, Shinichi KANOO, Kenji NOMA
  • Publication number: 20170040340
    Abstract: According to one embodiment, a semiconductor memory device includes a stacked body; a semiconductor body; and charge storage film. The stacked body includes the plurality of electrode layers separately stacked each other. The semiconductor body is provided in the stacked body and extends in a stack direction of the stacked body and includes an oxide semiconductor. The charge storage film is provided between the semiconductor body and the plurality of electrode layers.
    Type: Application
    Filed: October 20, 2016
    Publication date: February 9, 2017
    Inventors: Katsuaki NATORI, Masayuki TANAKA, Keiichi SAWA, Tetsuya KAI, Shinji MORI
  • Patent number: 9312271
    Abstract: According to an embodiment, a non-volatile memory device includes electrodes, an inter-layer insulating film between the electrodes and at least one semiconductor layer extending through the electrodes and the inter-layer insulating film. The device includes a charge storage layer between the semiconductor layer and each electrode, a first insulating film between the charge storage layer and the semiconductor layer, and a second insulating film. The second insulating film includes a first portion between the charge storage layer and each electrode, a second portion between each electrode and the inter-layer insulating film, and a third portion that links the first portion and the second portion. In a cross-section of the third portion parallel to the first direction and a second direction toward each electrode from the charge storage layer, a curved surface on the charge storage layer side has a curvature radius larger than a surface on the electrodes side.
    Type: Grant
    Filed: January 15, 2015
    Date of Patent: April 12, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Keiichi Sawa, Masayuki Tanaka, Katsuaki Natori
  • Publication number: 20160064406
    Abstract: According to one embodiment, a semiconductor memory device includes a stacked body; a semiconductor body; and charge storage film. The stacked body includes the plurality of electrode layers separately stacked each other. The semiconductor body is provided in the stacked body and extends in a stack direction of the stacked body and includes an oxide semiconductor. The charge storage film is provided between the semiconductor body and the plurality of electrode layers.
    Type: Application
    Filed: February 4, 2015
    Publication date: March 3, 2016
    Inventors: Katsuaki NATORI, Masayuki Tanaka, Keiichi Sawa, Tetsuya Kai, Shinji Mori
  • Publication number: 20160035740
    Abstract: According to an embodiment, a non-volatile memory device includes electrodes, an inter-layer insulating film between the electrodes and at least one semiconductor layer extending through the electrodes and the inter-layer insulating film. The device includes a charge storage layer between the semiconductor layer and each electrode, a first insulating film between the charge storage layer and the semiconductor layer, and a second insulating film. The second insulating film includes a first portion between the charge storage layer and each electrode, a second portion between each electrode and the inter-layer insulating film, and a third portion that links the first portion and the second portion. In a cross-section of the third portion parallel to the first direction and a second direction toward each electrode from the charge storage layer, a curved surface on the charge storage layer side has a curvature radius larger than a surface on the electrodes side.
    Type: Application
    Filed: January 15, 2015
    Publication date: February 4, 2016
    Inventors: Keiichi SAWA, Masayuki TANAKA, Katsuaki NATORI
  • Patent number: 9231192
    Abstract: According to one embodiment, a memory device with magnetroresistive effect element is disclosed. The element includes first metal magnetic film (MMF) with nonmagnetic element and axis of easy magnetization perpendicular (EMP), first insulating film, first intermediate magnetic film between the first MMF and the first insulating film, second MMF on the first insulating film and including nonmagnetic elements, the second MMF having axis of EMP, second intermediate magnetic film between the first insulating film and the second MMF, and diffusion preventing film including metal nitride having barrier property against diffusion of the nonmagnetic elements between the first MMF and the first intermediate magnetic film.
    Type: Grant
    Filed: January 6, 2014
    Date of Patent: January 5, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Daisuke Ikeno, Koji Yamakawa, Katsuaki Natori, Yasuyuki Sonoda
  • Patent number: 9196823
    Abstract: A magnetoresistive effect element includes the following structure. A first ferromagnetic layer has a variable magnetization direction. A second ferromagnetic layer has an invariable magnetization direction. A tunnel barrier layer is formed between the first and second ferromagnetic layers. An energy barrier between the first ferromagnetic layer and the tunnel barrier layer is higher than an energy barrier between the second ferromagnetic layer and the tunnel barrier layer. The second ferromagnetic layer contains a main component and an additive element. The main component contains at least one of Fe, Co, and Ni. The additive element contains at least one of Mg, Al, Ca, Sc, Ti, V, Mn, Zn, As, Sr, Y, Zr, Nb, Cd, In, Ba, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Hf, Ta, and W.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: November 24, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Makoto Nagamine, Daisuke Ikeno, Koji Ueda, Katsuya Nishiyama, Katsuaki Natori, Koji Yamakawa
  • Patent number: 9196335
    Abstract: According to one embodiment, a magnetic memory includes magnetoresistive effect elements each including a first magnetic layer, a tunnel barrier layer, and a second magnetic layer which are successively stacked, and a ferroelectric capacitor provided above the magnetoresistive effect elements via an insulating layer, and including a lower electrode, a ferroelectric film, and an upper electrode which are successively stacked.
    Type: Grant
    Filed: August 8, 2013
    Date of Patent: November 24, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Katsuaki Natori, Koji Yamakawa
  • Patent number: 9070866
    Abstract: According to one embodiment, a magnetoresistive effect element includes a first ferromagnetic layer, a tunnel barrier formed on the first ferromagnetic layer, and a second ferromagnetic layer formed on the tunnel barrier layer. The tunnel barrier includes a nonmagnetic oxide having a spinel structure. Oxides forming the spinel structure are combined such that a single phase is formed by a solid phase in a component ratio region including a component ratio corresponding to the spinel structure and having a width of not less than 2%.
    Type: Grant
    Filed: August 7, 2013
    Date of Patent: June 30, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Makoto Nagamine, Daisuke Ikeno, Katsuya Nishiyama, Katsuaki Natori, Koji Yamakawa
  • Patent number: 8982614
    Abstract: According to one embodiment, a magnetoresistive effect element includes a first ferromagnetic layer, a tunnel barrier provided on the first ferromagnetic layer, and a second ferromagnetic layer provided on the tunnel barrier. The tunnel barrier includes a nonmagnetic mixture containing MgO and a metal oxide with a composition which forms, in a solid phase, a single phase with MgO.
    Type: Grant
    Filed: August 8, 2013
    Date of Patent: March 17, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Makoto Nagamine, Daisuke Ikeno, Katsuya Nishiyama, Katsuaki Natori, Koji Yamakawa
  • Publication number: 20140284592
    Abstract: According to one embodiment, a magnetoresistive effect element includes a first ferromagnetic layer, a tunnel barrier provided on the first ferromagnetic layer, and a second ferromagnetic layer provided on the tunnel barrier. The tunnel barrier includes a nonmagnetic mixture containing MgO and a metal oxide with a composition which forms, in a solid phase, a single phase with MgO.
    Type: Application
    Filed: August 8, 2013
    Publication date: September 25, 2014
    Inventors: Makoto NAGAMINE, Daisuke IKENO, Katsuya NISHIYAMA, Katsuaki NATORI, Koji YAMAKAWA
  • Publication number: 20140284732
    Abstract: According to one embodiment, a magnetoresistive effect element includes a first ferromagnetic layer, a tunnel barrier formed on the first ferromagnetic layer, and a second ferromagnetic layer formed on the tunnel barrier layer. The tunnel barrier includes a nonmagnetic oxide having a spinel structure. Oxides forming the spinel structure are combined such that a single phase is formed by a solid phase in a component ratio region including a component ratio corresponding to the spinel structure and having a width of not less than 2%.
    Type: Application
    Filed: August 7, 2013
    Publication date: September 25, 2014
    Inventors: Makoto NAGAMINE, Daisuke IKENO, Katsuya NISHIYAMA, Katsuaki NATORI, Koji YAMAKAWA
  • Publication number: 20140269033
    Abstract: According to one embodiment, a magnetic memory includes magnetoresistive effect elements each including a first magnetic layer, a tunnel barrier layer, and a second magnetic layer which are successively stacked, and a ferroelectric capacitor provided above the magnetoresistive effect elements via an insulating layer, and including a lower electrode, a ferroelectric film, and an upper electrode which are successively stacked.
    Type: Application
    Filed: August 8, 2013
    Publication date: September 18, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Katsuaki NATORI, Koji YAMAKAWA
  • Patent number: 8741161
    Abstract: According to one embodiment, a method of manufacturing a semiconductor device, the method includes forming a pillar on a base layer, forming a insulating layer on the base layer to cover the pillar by using GCIB method, where a lowermost portion of an upper surface of the insulating layer is lower than an upper surface of the pillar, and polishing the insulating layer and the pillar to expose a head of the pillar by using CMP method, where an end point of the polishing is the lowermost portion of the upper surface of the insulating layer.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: June 3, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuyuki Sonoda, Kyoichi Suguro, Masatoshi Yoshikawa, Koji Yamakawa, Katsuaki Natori, Daisuke Ikeno
  • Publication number: 20140117478
    Abstract: According to one embodiment, a memory device with magnetroresistive effect element is disclosed. The element includes first metal magnetic film (MMF) with nonmagnetic element and axis of easy magnetization perpendicular (EMP), first insulating film, first intermediate magnetic film between the first MMF and the first insulating film, second MMF on the first insulating film and including nonmagnetic elements, the second MMF having axis of EMP, second intermediate magnetic film between the first insulating film and the second MMF, and diffusion preventing film including metal nitride having barrier property against diffusion of the nonmagnetic elements between the first MMF and the first intermediate magnetic film.
    Type: Application
    Filed: January 6, 2014
    Publication date: May 1, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Daisuke Ikeno, Koji Yamakawa, Katsuaki Natori, Yasuyuki Sonoda