Patents by Inventor Katsuhiko Hieda

Katsuhiko Hieda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10415011
    Abstract: The invention is an adherend recovery method capable of recovering adherends such as cells no matter the types of adherends. An adherend recovery method for recovering an adherend from a support includes exposing a stack disposed on the support, the stack including a photosensitive gas generation layer, an adhesive layer and the adherend in this order on the support, generating a gas from the photosensitive gas generation layer by the exposure to separate the support and the stack from each other by the action of the gas, and recovering the adherend from the support by recovering the stack separated.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: September 17, 2019
    Assignee: JSR CORPORATION
    Inventors: Katsuhiko Hieda, Tsutomu Shimokawa, Hiroto Kubo, Takashi Doi
  • Publication number: 20160168532
    Abstract: The invention is an adherend recovery method capable of recovering adherends such as cells no matter the types of adherends. An adherend recovery method for recovering an adherend from a support includes exposing a stack disposed on the support, the stack including a photosensitive gas generation layer, an adhesive layer and the adherend in this order on the support, generating a gas from the photosensitive gas generation layer by the exposure to separate the support and the stack from each other by the action of the gas, and recovering the adherend from the support by recovering the stack separated.
    Type: Application
    Filed: February 24, 2016
    Publication date: June 16, 2016
    Applicant: JSR CORPORATION
    Inventors: Katsuhiko HIEDA, Tsutomu SHIMOKAWA, Hiroto KUBO, Takashi DOI
  • Publication number: 20160136638
    Abstract: The invention is a microfluidic devices having a channel that is microscopic but is free from the risk of the attachment of substrates. A microfluidic device includes a channel in a body, and the channel has a patterned resin composition layer formed from a photosensitive resin composition including an oxiranyl group-containing compound, an oxetanyl group-containing compound and a photoacid generator.
    Type: Application
    Filed: January 21, 2016
    Publication date: May 19, 2016
    Applicant: JSR CORPORATION
    Inventors: Katsuhiko Hieda, Katsumi Inomata, Tomokazu Miyazaki, Takashi Doi, Hiroto Kubo
  • Publication number: 20120288747
    Abstract: The object of the present invention is to provide an electrochemical device, by which short circuit between electrode sheets can be prevented even when the electrode sheets come into contact with each other due to misregistration upon folding of the electrode sheets. The electrochemical device of the present invention is an electrochemical device having a electrode unit with a pair of band-like electrode sheets respectively folded so as to be alternately stacked in a state that the following respective electrode layers come into no contact with each other, wherein the pair of the electrode sheets each have a band-like current collector, a plurality of electrode layers respectively formed on plane regions surrounded by peripheral edge portions and folding edge portions in at least one surface of the current collector, and insulating films formed on respective both surfaces of the peripheral edge portions and folding edge portions in the current collector.
    Type: Application
    Filed: January 18, 2011
    Publication date: November 15, 2012
    Applicant: JSR Corporation
    Inventors: Masaya Naoi, Katsuhiko Hieda, Kinji Yamada
  • Patent number: 8119196
    Abstract: A semiconductor manufacturing apparatus comprises a discharge portion discharging a coating liquid onto a substrate; a gas supply tube supplying an inert gas into a liquid container that contains the coating liquid, and pressurizing an interior of the liquid container; a coating liquid supply tube airtightly supplying the coating liquid from the liquid container to the discharge portion using pressurization from the gas supply tube; a first connecting portion capable of attaching and detaching the liquid container to and from the coating liquid supply tube; a second connecting portion capable of attaching and detaching the liquid container to and from the gas supply tube; and a solvent supply tube supplying a solvent, which can dissolve the coating liquid, to the first connecting portion.
    Type: Grant
    Filed: February 24, 2010
    Date of Patent: February 21, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Osamu Arisumi, Masahiro Kiyotoshi, Katsuhiko Hieda
  • Publication number: 20110123936
    Abstract: A resist pattern coating agent includes a hydroxyl group-containing resin, a solvent, and at least two compounds including at least two groups shown by a following formula (1), compounds including a group shown by a following formula (2), and compounds including a group shown by a following formula (4).
    Type: Application
    Filed: February 7, 2011
    Publication date: May 26, 2011
    Applicant: JSR Corporation
    Inventors: Masafumi HORI, Michihiro Mita, Kouichi Fujiwara, Katsuhiko Hieda, Yoshikazu Yamaguchi, Tomohiro Kakizawa
  • Patent number: 7759174
    Abstract: A semiconductor device includes a substrate including a semiconductor and a trench, and an electrically rewritable semiconductor memory cell on the substrate, the semiconductor memory cell comprising a charge storage layer including an upper surface and a lower surface, an area of the lower surface being smaller than an area of the upper surface, and at least a part of the charge storage layer being provided in the trench, first insulating layer between the lower surface of the charge storage layer and a bottom surface of the trench, second insulating layer between a side surface of the trench and a side surface of the charge storage layer and between the side surface of the trench and a side surface of the first insulating layer, third insulating layer on the charge storage layer, and a control gate electrode on the third insulating layer.
    Type: Grant
    Filed: January 24, 2007
    Date of Patent: July 20, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Katsuhiko Hieda
  • Publication number: 20100159710
    Abstract: A semiconductor manufacturing apparatus comprises a discharge portion discharging a coating liquid onto a substrate; a gas supply tube supplying an inert gas into a liquid container that contains the coating liquid, and pressurizing an interior of the liquid container; a coating liquid supply tube airtightly supplying the coating liquid from the liquid container to the discharge portion using pressurization from the gas supply tube; a first connecting portion capable of attaching and detaching the liquid container to and from the coating liquid supply tube; a second connecting portion capable of attaching and detaching the liquid container to and from the gas supply tube; and a solvent supply tube supplying a solvent, which can dissolve the coating liquid, to the first connecting portion.
    Type: Application
    Filed: February 24, 2010
    Publication date: June 24, 2010
    Inventors: Osamu Arisumi, Masahiro Kiyotoshi, Katsuhiko Hieda
  • Publication number: 20100055869
    Abstract: A method of manufacturing a semiconductor device comprises forming a trench in a semiconductor substrate, forming a first insulating film having a first recessed portion in the trench, forming a coating film so as to fill the first recessed portion therewith, transforming the coating film into a second insulating film, planarizing the second insulating film to expose the first insulating film and the second insulating film, removing at least the second insulating film from the first recessed portion to moderate an aspect ratio for the first recessed portion formed in the trench, thereby forming a second recessed portion therein, and forming a third insulating film on a surface of the semiconductor substrate so as to fill the second recessed portion therewith.
    Type: Application
    Filed: October 2, 2009
    Publication date: March 4, 2010
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Osamu Arisumi, Masahiro Kiyotoshi, Katsuhiko Hieda, Yoshitaka Tsunashima
  • Patent number: 7618876
    Abstract: A method of manufacturing a semiconductor device comprises forming a trench in a semiconductor substrate, forming a first insulating film having a first recessed portion in the trench, forming a coating film so as to fill the first recessed portion therewith, transforming the coating film into a second insulating film, planarizing the second insulating film to expose the first insulating film and the second insulating film, removing at least the second insulating film from the first recessed portion to moderate an aspect ratio for the first recessed portion formed in the trench, thereby forming a second recessed portion therein, and forming a third insulating film on a surface of the semiconductor substrate so as to fill the second recessed portion therewith.
    Type: Grant
    Filed: September 16, 2005
    Date of Patent: November 17, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Osamu Arisumi, Masahiro Kiyotoshi, Katsuhiko Hieda, Yoshitaka Tsunashima
  • Patent number: 7579241
    Abstract: A semiconductor device comprises a semiconductor substrate, an electrically rewritable semiconductor memory cell provided on the semiconductor substrate, the memory cell comprising an island semiconductor portion provided on the surface of the semiconductor substrate or above the semiconductor substrate, a first insulating film provided on a top surface of the island semiconductor portion, a second insulating film provided on a side surface of the island semiconductor portion and being smaller in thickness than the first insulating film, and a charge storage layer provided on the side surface of the island semiconductor portion with the second insulating film interposed therebetween and on a side surface of the first insulating film, a third insulating film provided on the charge storage layer, and a control gate electrode provided on the third insulating film.
    Type: Grant
    Filed: April 25, 2007
    Date of Patent: August 25, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuhiko Hieda, Daisuke Hagishima
  • Patent number: 7416987
    Abstract: According to the present invention, there is a provided a semiconductor device fabrication method having, forming a mask material in a surface portion of a semiconductor substrate, and forming a step having a projection by using the mask material; forming a dielectric film on the semiconductor substrate so as to fill the step and planarize an entire surface; annealing the dielectric film; etching back the dielectric film such that a surface of the dielectric film is positioned between upper and lower surfaces of the mask material; and removing the mask material to expose a surface of the projection of the semiconductor substrate.
    Type: Grant
    Filed: June 22, 2006
    Date of Patent: August 26, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuhiko Hieda, Masahiro Kiyotoshi
  • Patent number: 7413987
    Abstract: There is disclosed a method of manufacturing a semiconductor device, wherein an Si3N4 film is formed as a mask member on the surface of a silicon substrate, then etched to form an STI trench. A solution of perhydrogenated silazane polymer is coated on the surface of the silicon substrate having an STI trench formed thereon to deposit a coated film (PSZ film) thereon. The PSZ film deposited on the mask member is removed, leaving part of the PSZ film inside the trench, wherein the thickness of the PSZ film is controlled to make the height thereof from the bottom of the STI trench become 600 nm or less. Thereafter, the PSZ film is heat-treated in a water vapor-containing atmosphere to convert the PSZ film into a silicon oxide film through a chemical reaction of the PSZ film. Subsequently, the silicon oxide film is heat-treated to densify the silicon oxide film.
    Type: Grant
    Filed: May 10, 2006
    Date of Patent: August 19, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuhiko Hieda, Atsuko Kawasaki, Masahiro Kiyotoshi, Katsuhiko Tachibana, Soichi Yamazaki
  • Publication number: 20080129970
    Abstract: An immersion exposure system 1 performs an exposure process through a liquid 301 provided between an optical element of a projection optical means 121 and a substrate 111. The immersion exposure system 1 includes a liquid supply section 80 which supplies the liquid 301, an exposure section to which the liquid 301 (301b) supplied from the liquid supply section 80 is continuously introduced along a specific direction and which performs an exposure process in a state in which a space between the optical element of the projection optical means 121 and the substrate 111 is filled with the liquid 301, a liquid recovery section 90 which recovers the liquid 301 (301a) passed through the exposure section 110 at a symmetrical position against the substrate 111, and a liquid recycling section 20 which recycles the liquid 301 (301c) recovered by the liquid recovery section 90.
    Type: Application
    Filed: January 20, 2006
    Publication date: June 5, 2008
    Inventors: Taiichi Furukawa, Katsuhiko Hieda, Yakashi Miyamatsu, Yong Wang, Kinji Yamada
  • Publication number: 20070287245
    Abstract: A semiconductor device comprises a semiconductor substrate, an electrically rewritable semiconductor memory cell provided on the semiconductor substrate, the memory cell comprising an island semiconductor portion provided on the surface of the semiconductor substrate or above the semiconductor substrate, a first insulating film provided on a top surface of the island semiconductor portion, a second insulating film provided on a side surface of the island semiconductor portion and being smaller in thickness than the first insulating film, and a charge storage layer provided on the side surface of the island semiconductor portion with the second insulating film interposed therebetween and on a side surface of the first insulating film, a third insulating film provided on the charge storage layer, and a control gate electrode provided on the third insulating film.
    Type: Application
    Filed: April 25, 2007
    Publication date: December 13, 2007
    Inventors: Katsuhiko Hieda, Daisuke Hagishima
  • Patent number: 7253075
    Abstract: A semiconductor device has a plurality of capacitors. The semiconductor device includes a first capacitor arranged on a substrate and including first upper and lower electrode layers between which a first capacitor insulation film is interposed, and a second capacitor arranged on the substrate and including second upper and lower electrode layers between which a second capacitor insulation film is interposed, the second upper and lower electrode layers having a same structure as that of the first upper and lower electrode layers, and the second capacitor having a per-unit-area capacity different from that of the first capacitor.
    Type: Grant
    Filed: July 9, 2004
    Date of Patent: August 7, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Katsuhiko Hieda
  • Publication number: 20070122946
    Abstract: A semiconductor device includes a substrate including a semiconductor and a trench, and an electrically rewritable semiconductor memory cell on the substrate, the semiconductor memory cell comprising a charge storage layer including an upper surface and a lower surface, an area of the lower surface being smaller than an area of the upper surface, and at least a part of the charge storage layer being provided in the trench, first insulating layer between the lower surface of the charge storage layer and a bottom surface of the trench, second insulating layer between a side surface of the trench and a side surface of the charge storage layer and between the side surface of the trench and a side surface of the first insulating layer, third insulating layer on the charge storage layer, and a control gate electrode on the third insulating layer.
    Type: Application
    Filed: January 24, 2007
    Publication date: May 31, 2007
    Inventor: Katsuhiko Hieda
  • Patent number: 7224019
    Abstract: A semiconductor device comprises a semiconductor substrate, an electrically rewritable semiconductor memory cell provided on the semiconductor substrate, the memory cell comprising an island semiconductor portion provided on the surface of the semiconductor substrate or above the semiconductor substrate, a first insulating film provided on a top surface of the island semiconductor portion, a second insulating film provided on a side surface of the island semiconductor portion and being smaller in thickness than the first insulating film, and a charge storage layer provided on the side surface of the island semiconductor portion with the second insulating film interposed therebetween and on a side surface of the first insulating film, a third insulating film provided on the charge storage layer, and a control gate electrode provided on the third insulating film.
    Type: Grant
    Filed: February 24, 2005
    Date of Patent: May 29, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuhiko Hieda, Daisuke Hagishima
  • Publication number: 20070066005
    Abstract: According to the present invention, there is a provided a semiconductor device fabrication method having, forming a mask material in a surface portion of a semiconductor substrate, and forming a step having a projection by using the mask material; forming a dielectric film on the semiconductor substrate so as to fill the step and planarize an entire surface; annealing the dielectric film; etching back the dielectric film such that a surface of the dielectric film is positioned between upper and lower surfaces of the mask material; and removing the mask material to expose a surface of the projection of the semiconductor substrate.
    Type: Application
    Filed: June 22, 2006
    Publication date: March 22, 2007
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Katsuhiko Hieda, Masahiro Kiyotoshi
  • Patent number: 7180121
    Abstract: A semiconductor device includes a substrate including a semiconductor and a trench, and an electrically rewritable semiconductor memory cell on the substrate, the semiconductor memory cell comprising a charge storage layer including an upper surface and a lower surface, an area of the lower surface being smaller than an area of the upper surface, and at least a part of the charge storage layer being provided in the trench, first insulating layer between the lower surface of the charge storage layer and a bottom surface of the trench, second insulating layer between a side surface of the trench and a side surface of the charge storage layer and between the side surface of the trench and a side surface of the first insulating layer, third insulating layer on the charge storage layer, and a control gate electrode on the third insulating layer.
    Type: Grant
    Filed: March 22, 2005
    Date of Patent: February 20, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Katsuhiko Hieda