Patents by Inventor Katsuhiko Hieda
Katsuhiko Hieda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10415011Abstract: The invention is an adherend recovery method capable of recovering adherends such as cells no matter the types of adherends. An adherend recovery method for recovering an adherend from a support includes exposing a stack disposed on the support, the stack including a photosensitive gas generation layer, an adhesive layer and the adherend in this order on the support, generating a gas from the photosensitive gas generation layer by the exposure to separate the support and the stack from each other by the action of the gas, and recovering the adherend from the support by recovering the stack separated.Type: GrantFiled: February 24, 2016Date of Patent: September 17, 2019Assignee: JSR CORPORATIONInventors: Katsuhiko Hieda, Tsutomu Shimokawa, Hiroto Kubo, Takashi Doi
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Publication number: 20160168532Abstract: The invention is an adherend recovery method capable of recovering adherends such as cells no matter the types of adherends. An adherend recovery method for recovering an adherend from a support includes exposing a stack disposed on the support, the stack including a photosensitive gas generation layer, an adhesive layer and the adherend in this order on the support, generating a gas from the photosensitive gas generation layer by the exposure to separate the support and the stack from each other by the action of the gas, and recovering the adherend from the support by recovering the stack separated.Type: ApplicationFiled: February 24, 2016Publication date: June 16, 2016Applicant: JSR CORPORATIONInventors: Katsuhiko HIEDA, Tsutomu SHIMOKAWA, Hiroto KUBO, Takashi DOI
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Publication number: 20160136638Abstract: The invention is a microfluidic devices having a channel that is microscopic but is free from the risk of the attachment of substrates. A microfluidic device includes a channel in a body, and the channel has a patterned resin composition layer formed from a photosensitive resin composition including an oxiranyl group-containing compound, an oxetanyl group-containing compound and a photoacid generator.Type: ApplicationFiled: January 21, 2016Publication date: May 19, 2016Applicant: JSR CORPORATIONInventors: Katsuhiko Hieda, Katsumi Inomata, Tomokazu Miyazaki, Takashi Doi, Hiroto Kubo
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Publication number: 20120288747Abstract: The object of the present invention is to provide an electrochemical device, by which short circuit between electrode sheets can be prevented even when the electrode sheets come into contact with each other due to misregistration upon folding of the electrode sheets. The electrochemical device of the present invention is an electrochemical device having a electrode unit with a pair of band-like electrode sheets respectively folded so as to be alternately stacked in a state that the following respective electrode layers come into no contact with each other, wherein the pair of the electrode sheets each have a band-like current collector, a plurality of electrode layers respectively formed on plane regions surrounded by peripheral edge portions and folding edge portions in at least one surface of the current collector, and insulating films formed on respective both surfaces of the peripheral edge portions and folding edge portions in the current collector.Type: ApplicationFiled: January 18, 2011Publication date: November 15, 2012Applicant: JSR CorporationInventors: Masaya Naoi, Katsuhiko Hieda, Kinji Yamada
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Patent number: 8119196Abstract: A semiconductor manufacturing apparatus comprises a discharge portion discharging a coating liquid onto a substrate; a gas supply tube supplying an inert gas into a liquid container that contains the coating liquid, and pressurizing an interior of the liquid container; a coating liquid supply tube airtightly supplying the coating liquid from the liquid container to the discharge portion using pressurization from the gas supply tube; a first connecting portion capable of attaching and detaching the liquid container to and from the coating liquid supply tube; a second connecting portion capable of attaching and detaching the liquid container to and from the gas supply tube; and a solvent supply tube supplying a solvent, which can dissolve the coating liquid, to the first connecting portion.Type: GrantFiled: February 24, 2010Date of Patent: February 21, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Osamu Arisumi, Masahiro Kiyotoshi, Katsuhiko Hieda
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Publication number: 20110123936Abstract: A resist pattern coating agent includes a hydroxyl group-containing resin, a solvent, and at least two compounds including at least two groups shown by a following formula (1), compounds including a group shown by a following formula (2), and compounds including a group shown by a following formula (4).Type: ApplicationFiled: February 7, 2011Publication date: May 26, 2011Applicant: JSR CorporationInventors: Masafumi HORI, Michihiro Mita, Kouichi Fujiwara, Katsuhiko Hieda, Yoshikazu Yamaguchi, Tomohiro Kakizawa
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Patent number: 7759174Abstract: A semiconductor device includes a substrate including a semiconductor and a trench, and an electrically rewritable semiconductor memory cell on the substrate, the semiconductor memory cell comprising a charge storage layer including an upper surface and a lower surface, an area of the lower surface being smaller than an area of the upper surface, and at least a part of the charge storage layer being provided in the trench, first insulating layer between the lower surface of the charge storage layer and a bottom surface of the trench, second insulating layer between a side surface of the trench and a side surface of the charge storage layer and between the side surface of the trench and a side surface of the first insulating layer, third insulating layer on the charge storage layer, and a control gate electrode on the third insulating layer.Type: GrantFiled: January 24, 2007Date of Patent: July 20, 2010Assignee: Kabushiki Kaisha ToshibaInventor: Katsuhiko Hieda
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Publication number: 20100159710Abstract: A semiconductor manufacturing apparatus comprises a discharge portion discharging a coating liquid onto a substrate; a gas supply tube supplying an inert gas into a liquid container that contains the coating liquid, and pressurizing an interior of the liquid container; a coating liquid supply tube airtightly supplying the coating liquid from the liquid container to the discharge portion using pressurization from the gas supply tube; a first connecting portion capable of attaching and detaching the liquid container to and from the coating liquid supply tube; a second connecting portion capable of attaching and detaching the liquid container to and from the gas supply tube; and a solvent supply tube supplying a solvent, which can dissolve the coating liquid, to the first connecting portion.Type: ApplicationFiled: February 24, 2010Publication date: June 24, 2010Inventors: Osamu Arisumi, Masahiro Kiyotoshi, Katsuhiko Hieda
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Publication number: 20100055869Abstract: A method of manufacturing a semiconductor device comprises forming a trench in a semiconductor substrate, forming a first insulating film having a first recessed portion in the trench, forming a coating film so as to fill the first recessed portion therewith, transforming the coating film into a second insulating film, planarizing the second insulating film to expose the first insulating film and the second insulating film, removing at least the second insulating film from the first recessed portion to moderate an aspect ratio for the first recessed portion formed in the trench, thereby forming a second recessed portion therein, and forming a third insulating film on a surface of the semiconductor substrate so as to fill the second recessed portion therewith.Type: ApplicationFiled: October 2, 2009Publication date: March 4, 2010Applicant: Kabushiki Kaisha ToshibaInventors: Osamu Arisumi, Masahiro Kiyotoshi, Katsuhiko Hieda, Yoshitaka Tsunashima
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Patent number: 7618876Abstract: A method of manufacturing a semiconductor device comprises forming a trench in a semiconductor substrate, forming a first insulating film having a first recessed portion in the trench, forming a coating film so as to fill the first recessed portion therewith, transforming the coating film into a second insulating film, planarizing the second insulating film to expose the first insulating film and the second insulating film, removing at least the second insulating film from the first recessed portion to moderate an aspect ratio for the first recessed portion formed in the trench, thereby forming a second recessed portion therein, and forming a third insulating film on a surface of the semiconductor substrate so as to fill the second recessed portion therewith.Type: GrantFiled: September 16, 2005Date of Patent: November 17, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Osamu Arisumi, Masahiro Kiyotoshi, Katsuhiko Hieda, Yoshitaka Tsunashima
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Patent number: 7579241Abstract: A semiconductor device comprises a semiconductor substrate, an electrically rewritable semiconductor memory cell provided on the semiconductor substrate, the memory cell comprising an island semiconductor portion provided on the surface of the semiconductor substrate or above the semiconductor substrate, a first insulating film provided on a top surface of the island semiconductor portion, a second insulating film provided on a side surface of the island semiconductor portion and being smaller in thickness than the first insulating film, and a charge storage layer provided on the side surface of the island semiconductor portion with the second insulating film interposed therebetween and on a side surface of the first insulating film, a third insulating film provided on the charge storage layer, and a control gate electrode provided on the third insulating film.Type: GrantFiled: April 25, 2007Date of Patent: August 25, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Katsuhiko Hieda, Daisuke Hagishima
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Patent number: 7416987Abstract: According to the present invention, there is a provided a semiconductor device fabrication method having, forming a mask material in a surface portion of a semiconductor substrate, and forming a step having a projection by using the mask material; forming a dielectric film on the semiconductor substrate so as to fill the step and planarize an entire surface; annealing the dielectric film; etching back the dielectric film such that a surface of the dielectric film is positioned between upper and lower surfaces of the mask material; and removing the mask material to expose a surface of the projection of the semiconductor substrate.Type: GrantFiled: June 22, 2006Date of Patent: August 26, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Katsuhiko Hieda, Masahiro Kiyotoshi
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Patent number: 7413987Abstract: There is disclosed a method of manufacturing a semiconductor device, wherein an Si3N4 film is formed as a mask member on the surface of a silicon substrate, then etched to form an STI trench. A solution of perhydrogenated silazane polymer is coated on the surface of the silicon substrate having an STI trench formed thereon to deposit a coated film (PSZ film) thereon. The PSZ film deposited on the mask member is removed, leaving part of the PSZ film inside the trench, wherein the thickness of the PSZ film is controlled to make the height thereof from the bottom of the STI trench become 600 nm or less. Thereafter, the PSZ film is heat-treated in a water vapor-containing atmosphere to convert the PSZ film into a silicon oxide film through a chemical reaction of the PSZ film. Subsequently, the silicon oxide film is heat-treated to densify the silicon oxide film.Type: GrantFiled: May 10, 2006Date of Patent: August 19, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Katsuhiko Hieda, Atsuko Kawasaki, Masahiro Kiyotoshi, Katsuhiko Tachibana, Soichi Yamazaki
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Publication number: 20080129970Abstract: An immersion exposure system 1 performs an exposure process through a liquid 301 provided between an optical element of a projection optical means 121 and a substrate 111. The immersion exposure system 1 includes a liquid supply section 80 which supplies the liquid 301, an exposure section to which the liquid 301 (301b) supplied from the liquid supply section 80 is continuously introduced along a specific direction and which performs an exposure process in a state in which a space between the optical element of the projection optical means 121 and the substrate 111 is filled with the liquid 301, a liquid recovery section 90 which recovers the liquid 301 (301a) passed through the exposure section 110 at a symmetrical position against the substrate 111, and a liquid recycling section 20 which recycles the liquid 301 (301c) recovered by the liquid recovery section 90.Type: ApplicationFiled: January 20, 2006Publication date: June 5, 2008Inventors: Taiichi Furukawa, Katsuhiko Hieda, Yakashi Miyamatsu, Yong Wang, Kinji Yamada
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Publication number: 20070287245Abstract: A semiconductor device comprises a semiconductor substrate, an electrically rewritable semiconductor memory cell provided on the semiconductor substrate, the memory cell comprising an island semiconductor portion provided on the surface of the semiconductor substrate or above the semiconductor substrate, a first insulating film provided on a top surface of the island semiconductor portion, a second insulating film provided on a side surface of the island semiconductor portion and being smaller in thickness than the first insulating film, and a charge storage layer provided on the side surface of the island semiconductor portion with the second insulating film interposed therebetween and on a side surface of the first insulating film, a third insulating film provided on the charge storage layer, and a control gate electrode provided on the third insulating film.Type: ApplicationFiled: April 25, 2007Publication date: December 13, 2007Inventors: Katsuhiko Hieda, Daisuke Hagishima
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Patent number: 7253075Abstract: A semiconductor device has a plurality of capacitors. The semiconductor device includes a first capacitor arranged on a substrate and including first upper and lower electrode layers between which a first capacitor insulation film is interposed, and a second capacitor arranged on the substrate and including second upper and lower electrode layers between which a second capacitor insulation film is interposed, the second upper and lower electrode layers having a same structure as that of the first upper and lower electrode layers, and the second capacitor having a per-unit-area capacity different from that of the first capacitor.Type: GrantFiled: July 9, 2004Date of Patent: August 7, 2007Assignee: Kabushiki Kaisha ToshibaInventor: Katsuhiko Hieda
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Publication number: 20070122946Abstract: A semiconductor device includes a substrate including a semiconductor and a trench, and an electrically rewritable semiconductor memory cell on the substrate, the semiconductor memory cell comprising a charge storage layer including an upper surface and a lower surface, an area of the lower surface being smaller than an area of the upper surface, and at least a part of the charge storage layer being provided in the trench, first insulating layer between the lower surface of the charge storage layer and a bottom surface of the trench, second insulating layer between a side surface of the trench and a side surface of the charge storage layer and between the side surface of the trench and a side surface of the first insulating layer, third insulating layer on the charge storage layer, and a control gate electrode on the third insulating layer.Type: ApplicationFiled: January 24, 2007Publication date: May 31, 2007Inventor: Katsuhiko Hieda
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Patent number: 7224019Abstract: A semiconductor device comprises a semiconductor substrate, an electrically rewritable semiconductor memory cell provided on the semiconductor substrate, the memory cell comprising an island semiconductor portion provided on the surface of the semiconductor substrate or above the semiconductor substrate, a first insulating film provided on a top surface of the island semiconductor portion, a second insulating film provided on a side surface of the island semiconductor portion and being smaller in thickness than the first insulating film, and a charge storage layer provided on the side surface of the island semiconductor portion with the second insulating film interposed therebetween and on a side surface of the first insulating film, a third insulating film provided on the charge storage layer, and a control gate electrode provided on the third insulating film.Type: GrantFiled: February 24, 2005Date of Patent: May 29, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Katsuhiko Hieda, Daisuke Hagishima
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Publication number: 20070066005Abstract: According to the present invention, there is a provided a semiconductor device fabrication method having, forming a mask material in a surface portion of a semiconductor substrate, and forming a step having a projection by using the mask material; forming a dielectric film on the semiconductor substrate so as to fill the step and planarize an entire surface; annealing the dielectric film; etching back the dielectric film such that a surface of the dielectric film is positioned between upper and lower surfaces of the mask material; and removing the mask material to expose a surface of the projection of the semiconductor substrate.Type: ApplicationFiled: June 22, 2006Publication date: March 22, 2007Applicant: Kabushiki Kaisha ToshibaInventors: Katsuhiko Hieda, Masahiro Kiyotoshi
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Patent number: 7180121Abstract: A semiconductor device includes a substrate including a semiconductor and a trench, and an electrically rewritable semiconductor memory cell on the substrate, the semiconductor memory cell comprising a charge storage layer including an upper surface and a lower surface, an area of the lower surface being smaller than an area of the upper surface, and at least a part of the charge storage layer being provided in the trench, first insulating layer between the lower surface of the charge storage layer and a bottom surface of the trench, second insulating layer between a side surface of the trench and a side surface of the charge storage layer and between the side surface of the trench and a side surface of the first insulating layer, third insulating layer on the charge storage layer, and a control gate electrode on the third insulating layer.Type: GrantFiled: March 22, 2005Date of Patent: February 20, 2007Assignee: Kabushiki Kaisha ToshibaInventor: Katsuhiko Hieda